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#define | __dmb(i) __builtin_arm_dmb(i) |
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#define | __dsb(i) __builtin_arm_dsb(i) |
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#define | __isb(i) __builtin_arm_isb(i) |
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#define | __pld(addr) __pldx(0, 0, 0, addr) |
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#define | __pldx(access_kind, cache_level, retention_policy, addr) __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1) |
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#define | __pli(addr) __plix(0, 0, addr) |
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#define | __plix(cache_level, retention_policy, addr) __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0) |
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#define | __arm_rsr(sysreg) __builtin_arm_rsr(sysreg) |
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#define | __arm_rsr64(sysreg) __builtin_arm_rsr64(sysreg) |
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#define | __arm_rsrp(sysreg) __builtin_arm_rsrp(sysreg) |
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#define | __arm_wsr(sysreg, v) __builtin_arm_wsr(sysreg, v) |
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#define | __arm_wsr64(sysreg, v) __builtin_arm_wsr64(sysreg, v) |
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#define | __arm_wsrp(sysreg, v) __builtin_arm_wsrp(sysreg, v) |
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static __inline__ uint32_t
volatile uint32_t * | p |
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do | v = __builtin_arm_ldrex(p) |
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static __inline__ uint32_t uint32_t | y |
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#define __arm_rsr |
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sysreg | ) |
__builtin_arm_rsr(sysreg) |
#define __arm_rsr64 |
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sysreg | ) |
__builtin_arm_rsr64(sysreg) |
#define __arm_rsrp |
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sysreg | ) |
__builtin_arm_rsrp(sysreg) |
#define __arm_wsr |
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sysreg, |
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v |
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| __builtin_arm_wsr(sysreg, v) |
#define __arm_wsr64 |
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sysreg, |
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v |
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| __builtin_arm_wsr64(sysreg, v) |
#define __arm_wsrp |
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sysreg, |
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v |
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| __builtin_arm_wsrp(sysreg, v) |
#define __dmb |
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i | ) |
__builtin_arm_dmb(i) |
#define __dsb |
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i | ) |
__builtin_arm_dsb(i) |
#define __isb |
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i | ) |
__builtin_arm_isb(i) |
#define __pldx |
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access_kind, |
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cache_level, |
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retention_policy, |
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addr |
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| __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1) |
#define __plix |
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cache_level, |
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retention_policy, |
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addr |
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| __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0) |
while |
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__builtin_arm_strex(x, p) |
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__inline__ uint32_t volatile uint32_t* p |
Initial value:{
do v
Definition: arm_acle.h:77
static __inline__ unsigned long uint32_t y |
Initial value:{
static __inline__ uint32_t uint32_t y
Definition: arm_acle.h:113