enum Ucs_Stream_PortClockDataDelay_t

This setting is only applicable to data pins used for Generic Streaming including any linked pins to Streaming Port B. All data pins share the same FSY / SCK signals, hence this setting applies to all data pins.

Enumerator:

UCS_STREAM_PORT_CLK_DLY_NONE	Data is not delayed by a single SCK clock delay.
UCS_STREAM_PORT_CLK_DLY_DELAYED	There is a single SCK clock delay between the start of frame (falling edge of FSY) and the start of the frame data on the data pins.
UCS_STREAM_PORT_CLK_DLY_BDO	Bit delayed only. There is a single SCK clock delay between the start of frame (rising edge of FSY) and the start of the frame data on the data pins.
UCS_STREAM_PORT_CLK_DLY_WILD	Wildcard.