Index

Unhandled(NA)
A2W(0x7e102000) - Clock manager PLL control
APERF0(0x7e009800)
APERF1(0x7ee08000)
APHY_CSR(0x7ee06000) - SDRAM Adress (pin) control
ARM(0x7E00B000)
ASB(0x7e00a000)
AUX(0x7E215000)
AVE_IN(0x7e910000)
AVE_OUT(0x7e240000)
CAM0(0x7e800000)
CAM1(0x7e801000)
CCP2TX(0x7e001000)
CM(0x7e101000) - Clock manager
CMI(0x7e802000)
CPG(0x7e211000)
DMA(0x7e007fe0)
DMA0(0x7e007000)
DMA1(0x7e007100)
DMA10(0x7e007a00)
DMA11(0x7e007b00)
DMA12(0x7e007c00)
DMA13(0x7e007d00)
DMA14(0x7e007e00)
DMA15(0x7ee05000)
DMA2(0x7e007200)
DMA3(0x7e007300)
DMA4(0x7e007400)
DMA5(0x7e007500)
DMA6(0x7e007600)
DMA7(0x7e007700)
DMA8(0x7e007800)
DMA9(0x7e007900)
DPHY_CSR(0x7ee07000) - SDRAM Data (pin) control
DPI(0x7e208000)
DSI(0x7e209000)
DSI0(0x7e209000)
DSI1(0x7e700000)
EMMC(0x7e300000)
FPGA(0x7e20b600)
GP(0x7e200000) - GPIO control
H264(0x7f000000)
HD(0x7e808000)
HDCP(0x7e809000)
HDMI(0x7e902000)
I2C0(0x7e205000)
I2C1(0x7e804000)
I2C2(0x7e805000)
I2C_SPI_SLV(0x7e214000)
IC0(0x7e002000)
IC1(0x7e002800)
ISP(0x7ea00000)
JP(0x7e005000)
L1(0x7ee02000) - VC4-L1 control
L2(0x7ee01000) - VC4-L2 control
MPHI(0x7e006000)
MS(0x7e000000)
NU(0x7e008000)
OTP(0x7e20f000) - One Time programmable
PCM(0x7e203000)
PIARBCTL(0x7e80a000)
PIXELVALVE0(0x7e206000)
PIXELVALVE1(0x7e207000)
PIXELVALVE2(0x7e807000)
PM(0x7e100000) - Power manager
PRM(0x7e20d000)
PWM(0x7e20c000)
RNG(0x7e104000)
SCALER(0x7e400000)
SD(0x7ee00000) - SDRAM
SH(0x7e202000)
SLIM(0x7e210000)
SMI(0x7e600000)
SPI(0x7e204000)
ST(0x7e003000)
SYSAC(0x7e009000)
TB(0x7e20b000)
TE(0x7e20e000)
TS(0x7e212000)
TXP(0x7e004000)
UART(0x7e201000)
USB(0x7e980000)
V3D(0x7ec00000)
VCE(0x7f100000)
VEC(0x7e806000)
VPU_ARB_CTRL(0x7ee04000)

Unhandled

Info

base	NA

Registers

register name	address	type	width	mask	reset

Unsupported defines

define	value
ACISASR_REG	0x1c004814:RW
ACISCA_REG	0x1c004808:RW
ACISCD_REG	0x1c00480c:RW
ACISCS_REG	0x1c004800:RW
ACISFIFO_REG	0x1c004804:RW
ACISMODE_REG	0x1c004810:RW
ACIS_BASE_ADDRESS	0x1C004800
ACIS_DMA	0
AC_HUFFTABLE_OFFSET(t)	MACRO
AC_MAXCTABLE_OFFSET(t)	MACRO
AC_OSETTABLE_OFFSET(t)	MACRO
ADCCS_REG	0x1c00e000:RW
ADCR0_REG	0x1c00e004:RW
ADCR1_REG	0x1c00e008:RW
ADC_BASE_ADDRESS	0x1C00E000
ADC_DMA	0xf0000
ADDRESS_EXTERNAL(p)	MACRO
AJBCONF_REG	0x7e2000c0:RW
AJBTDI_REG	0x7e2000c8:RW
AJBTDO_REG	0x7e2000cc:RW
AJBTMS_REG	0x7e2000c4:RW
AJB_BITS0	0x000000
AJB_BITS12	0x00000C
AJB_BITS16	0x000010
AJB_BITS20	0x000014
AJB_BITS24	0x000018
AJB_BITS28	0x00001C
AJB_BITS32	0x000020
AJB_BITS34	0x000022
AJB_BITS4	0x000004
AJB_BITS8	0x000008
AJB_BUSY	0x80000000
AJB_CLKSHFT	16
AJB_D0_FALL	0x000000
AJB_D0_RISE	0x000100
AJB_D1_FALL	0x000000
AJB_D1_RISE	0x000200
AJB_ENABLE	0x000800
AJB_HOLD0	0x000000
AJB_HOLD1	0x001000
AJB_HOLD2	0x002000
AJB_HOLD3	0x003000
AJB_INV_CLK	0x000080
AJB_IN_FALL	0x000000
AJB_IN_RISE	0x000400
AJB_OUT_LS	0x000000
AJB_OUT_MS	0x000040
AJB_RESETN	0x004000
ALIAS_ANY_L1_NONALLOCATING(x)	MACRO
ALIAS_ANY_NONALLOCATING(x)	MACRO
ALIAS_ANY_NONALLOCATING_READ(x)	MACRO
ALIAS_COHERENT(x)	MACRO
ALIAS_DIRECT(x)	MACRO
ALIAS_L1L2_NONALLOCATING(x)	MACRO
ALIAS_L1L2_NONALLOCATING_READ(x)	MACRO
ALIAS_L1_NONALLOCATING(x)	MACRO
ALIAS_NORMAL(x)	MACRO
ALIAS_STREAMING(x)	MACRO
AM_DB_MEMPRI_REG	0x1800d014:RW
AM_DB_PERPRI_REG	0x1800d018:RW
AM_HO_MEMPRI_REG	0x1800d00c:RW
AM_HO_PERPRI_REG	0x1800d010:RW
AM_HVSM_PRI_REG	0x1800d01c:RW
AM_VP_L2_PRI_REG	0x1800d000:RW
AM_VP_PERPRI_REG	0x1800d008:RW
AM_VP_UC_PRI_REG	0x1800d004:RW
BIT_STREAM_DMA	0
BOOTROM_BASE_ADDRESS	0x10000000
BOOTROM_BRCTL_REG	0x1000c000:RW
BOOTROM_RAM_LENGTH	( 1024 * 2 )
BOOTROM_RAM_START	0x10008000
BOOTROM_ROM_LENGTH	( 1024 * 32 )
BOOTROM_ROM_START	0x10000000
CAM_DMA	0
CCP2RBC0_REG	CCP2_BASE_ADDRESS + 0x118:RO
CCP2RBC1_REG	CCP2_BASE_ADDRESS + 0x218:RO
CCP2RC0_REG	CCP2_BASE_ADDRESS + 0x100:RW
CCP2RC1_REG	CCP2_BASE_ADDRESS + 0x200:RW
CCP2RC_REG	CCP2_BASE_ADDRESS + 0x00:RW
CCP2RDEA0_REG	CCP2_BASE_ADDRESS + 0x124:RW
CCP2RDEA1_REG	CCP2_BASE_ADDRESS + 0x224:RW
CCP2RDR1_REG	CCP2_BASE_ADDRESS + 0x80:RO
CCP2RDR2_REG	CCP2_BASE_ADDRESS + 0x84:RO
CCP2RDR3_REG	CCP2_BASE_ADDRESS + 0x88:RO
CCP2RDS0_REG	CCP2_BASE_ADDRESS + 0x128:RW
CCP2RDS1_REG	CCP2_BASE_ADDRESS + 0x228:RW
CCP2RDSA0_REG	CCP2_BASE_ADDRESS + 0x120:RW
CCP2RDSA1_REG	CCP2_BASE_ADDRESS + 0x220:RW
CCP2REA0_REG	CCP2_BASE_ADDRESS + 0x110:RW
CCP2REA1_REG	CCP2_BASE_ADDRESS + 0x210:RW
CCP2RLS0_REG	CCP2_BASE_ADDRESS + 0x11C:RW
CCP2RLS1_REG	CCP2_BASE_ADDRESS + 0x21C:RW
CCP2RPC0_REG	CCP2_BASE_ADDRESS + 0x104:RW
CCP2RPC1_REG	CCP2_BASE_ADDRESS + 0x204:RW
CCP2RS0_REG	CCP2_BASE_ADDRESS + 0x108:RW
CCP2RS1_REG	CCP2_BASE_ADDRESS + 0x208:RW
CCP2RSA0_REG	CCP2_BASE_ADDRESS + 0x10C:RW
CCP2RSA1_REG	CCP2_BASE_ADDRESS + 0x20C:RW
CCP2RS_REG	CCP2_BASE_ADDRESS + 0x04:RW
CCP2RWP0_REG	CCP2_BASE_ADDRESS + 0x114:RO
CCP2RWP1_REG	CCP2_BASE_ADDRESS + 0x214:RO
CCP2TAC_REG	0x7e001008:RW
CCP2TBA_REG	0x7e00101c:RW
CCP2TC_REG	0x7e001000:RW
CCP2TDL_REG	0x7e001020:RW
CCP2TD_REG	0x7e001024:RW
CCP2TIC_REG	0x7e001014:RW
CCP2TPC_REG	0x7e00100c:RW
CCP2TSC_REG	0x7e001010:RW
CCP2TSPARE_REG	0x7e001028:RW
CCP2TS_REG	0x7e001004:RW
CCP2TTC_REG	0x7e001018:RW
CDPC_REG	0x1c00e000:RW
CDP_BASE	0x1C00E000
CDP_DEBUG0_REG	0x1c00e00c:RW
CDP_DEBUG1_REG	0x1c00e010:RW
CDP_PHYC_REG	0x1c00e004:RW
CDP_PHYTSTDAT_REG	0x1c00e008:RW
CGMSAE_BOT_CONTROL_REG	0x7e806048:RW
CGMSAE_BOT_DATA_REG	0x7e806058:RW
CGMSAE_BOT_FORMAT_REG	0x7e806050:RW
CGMSAE_RESET_REG	0x7e806040:RW
CGMSAE_REVID_REG	0x7e80605c:RW
CGMSAE_TOP_CONTROL_REG	0x7e806044:RW
CGMSAE_TOP_DATA_REG	0x7e806054:RW
CGMSAE_TOP_FORMAT_REG	0x7e80604c:RW
CLR_GPIO(g)	MACRO
CMACIS_REG	0x7C:RW
CMCAM_REG	0x7C:RW
CMCORE_REG	0x7C:RW
CMGEN_REG	0x7C:RW
CMLCD_REG	0x7C:RW
CMMSP_REG	0x7C:RW
CMNVT_REG	0x7C:RW
CMPCM_REG	0x7C:RW
CMPLL1_REG	0x7C:RW
CMPLL2_REG	0x7C:RW
CMPLL3_REG	0x7C:RW
CMPLLC_REG	0x7C:RW
CMPRE1_REG	0x7C:RW
CMPRE2_REG	0x7C:RW
CMPRE3_REG	0x7C:RW
CMPREC_REG	0x7C:RW
CMTIMERF_REG	0x7C:RW
CMTIMER_REG	0x7C:RW
CMUARTF_REG	0x7C:RW
CMUART_REG	0x7C:RW
CMUSB_REG	0x7C:RW
CRYPTO_IP_DMA	0x130000
CRYPTO_ISR_REG	0x7e00200c:RO
CRYPTO_ISR_RNG_INT	0x0100000
CRYPTO_OP_DMA	0x140000
CSI2DBGDPHY_REG	CSI2_BASE_ADDRESS + 0x80:RW
CSI2DBGMISC_REG	CSI2_BASE_ADDRESS + 0x84:RW
CSI2LPRX0_REG	CSI2_BASE_ADDRESS + 0x20:RW
CSI2LPRX1_REG	CSI2_BASE_ADDRESS + 0x24:RW
CSI2LPRX2_REG	CSI2_BASE_ADDRESS + 0x28:RW
CSI2LPRX3_REG	CSI2_BASE_ADDRESS + 0x2C:RW
CSI2LPRXC_REG	CSI2_BASE_ADDRESS + 0x30:RW
CSI2RDR3_REG	CSI2_BASE_ADDRESS + 0x94:RW
CSI2TRIG_REG	CSI2_BASE_ADDRESS + 0x40:RW
CSI2_DTOV0_REG	CSI2_BASE_ADDRESS + 0x12C:RW
CSI2_DTOV1_REG	CSI2_BASE_ADDRESS + 0x22C:RW
CSI2_DTOV_x(x)	MACRO
CSI2_RBC0_REG	CSI2_BASE_ADDRESS + 0x118:RW
CSI2_RBC1_REG	CSI2_BASE_ADDRESS + 0x218:RW
CSI2_RBC_x(x)	MACRO
CSI2_RC0_REG	CSI2_BASE_ADDRESS + 0x100:RW
CSI2_RC1_REG	CSI2_BASE_ADDRESS + 0x200:RW
CSI2_RC_REG	CSI2_BASE_ADDRESS + 0x00:RW
CSI2_RC_x(x)	MACRO
CSI2_RDEA0_REG	CSI2_BASE_ADDRESS + 0x124:RW
CSI2_RDEA1_REG	CSI2_BASE_ADDRESS + 0x224:RW
CSI2_RDEA_x(x)	MACRO
CSI2_RDLS_REG	CSI2_BASE_ADDRESS + 0x08:RW
CSI2_RDS0_REG	CSI2_BASE_ADDRESS + 0x128:RW
CSI2_RDS1_REG	CSI2_BASE_ADDRESS + 0x228:RW
CSI2_RDSA0_REG	CSI2_BASE_ADDRESS + 0x120:RW
CSI2_RDSA1_REG	CSI2_BASE_ADDRESS + 0x220:RW
CSI2_RDSA_x(x)	MACRO
CSI2_RDS_x(x)	MACRO
CSI2_REA0_REG	CSI2_BASE_ADDRESS + 0x110:RW
CSI2_REA1_REG	CSI2_BASE_ADDRESS + 0x210:RW
CSI2_REA_x(x)	MACRO
CSI2_RGSP_REG	CSI2_BASE_ADDRESS + 0x0C:RW
CSI2_RLS0_REG	CSI2_BASE_ADDRESS + 0x11C:RW
CSI2_RLS1_REG	CSI2_BASE_ADDRESS + 0x21C:RW
CSI2_RLS_x(x)	MACRO
CSI2_RPC0_REG	CSI2_BASE_ADDRESS + 0x104:RW
CSI2_RPC1_REG	CSI2_BASE_ADDRESS + 0x204:RW
CSI2_RPC_x(x)	MACRO
CSI2_RS0_REG	CSI2_BASE_ADDRESS + 0x108:RW
CSI2_RS1_REG	CSI2_BASE_ADDRESS + 0x208:RW
CSI2_RSA0_REG	CSI2_BASE_ADDRESS + 0x10C:RW
CSI2_RSA1_REG	CSI2_BASE_ADDRESS + 0x20C:RW
CSI2_RSA_x(x)	MACRO
CSI2_RS_REG	CSI2_BASE_ADDRESS + 0x04:RW
CSI2_RS_x(x)	MACRO
CSI2_RWP0_REG	CSI2_BASE_ADDRESS + 0x114:RW
CSI2_RWP1_REG	CSI2_BASE_ADDRESS + 0x214:RW
CSI2_RWP_x(x)	MACRO
CSI2_SRST_REG	CSI2_BASE_ADDRESS + 0x90:RW
CSI2_THSCKTO_REG	CSI2_BASE_ADDRESS + 0x1C:RW
CSI2_THSSET_REG	CSI2_BASE_ADDRESS + 0x18:RW
CSI2_THSSTO_REG	CSI2_BASE_ADDRESS + 0x14:RW
CSI2_TREN_REG	CSI2_BASE_ADDRESS + 0x10:RW
D1CACHE_BASE_REG	0xffffffff:RW
DC0CS_REG	0x7ee02100:RW
DC0END_REG	0x7ee02108:RW
DC0START_REG	0x7ee02104:RW
DC1CS_REG	0xffffffff:RW
DC1END_REG	0xffffffff:RW
DC1START_REG	0xffffffff:RW
DC_HUFFTABLE_OFFSET(t)	MACRO
DC_MAXCTABLE_OFFSET(t)	MACRO
DC_OSETTABLE_OFFSET(t)	MACRO
DISPC_BASE_ADDRESS	0x1C009000
DISP_DMA	0
DSI2_DMA	0x100000
DUMMYREG_REG	0x7C:RW
GPAFEN0_REG	0x7e200088:RW
GPAFEN1_REG	0x7e20008c:RW
GPAFEN2_REG	0x7e200090:RW
GPAREN0_REG	0x7e20007c:RW
GPAREN1_REG	0x7e200080:RW
GPAREN2_REG	0x7e200084:RW
GPCLR0_REG	0x7e200028:RW
GPCLR1_REG	0x7e20002c:RW
GPCLR2_REG	0x7e200030:RW
GPEDS0_REG	0x7e200040:RW
GPEDS1_REG	0x7e200044:RW
GPEDS2_REG	0x7e200048:RW
GPFEN0_REG	0x7e200058:RW
GPFEN1_REG	0x7e20005c:RW
GPFEN2_REG	0x7e200060:RW
GPFSEL0_REG	0x7e200000:RW
GPFSEL1_REG	0x7e200004:RW
GPFSEL2_REG	0x7e200008:RW
GPFSEL3_REG	0x7e20000c:RW
GPFSEL4_REG	0x7e200010:RW
GPFSEL5_REG	0x7e200014:RW
GPFSEL6_REG	0x7e200018:RW
GPHEN0_REG	0x7e200064:RW
GPHEN1_REG	0x7e200068:RW
GPHEN2_REG	0x7e20006c:RW
GPIO_MAX_PINS	54
GPLEN0_REG	0x7e200070:RW
GPLEN1_REG	0x7e200074:RW
GPLEN2_REG	0x7e200078:RW
GPLEV0_REG	0x7e200034:RW
GPLEV1_REG	0x7e200038:RW
GPLEV2_REG	0x7e20003c:RW
GPPUDCLK0_REG	0x7e200098:RW
GPPUDCLK1_REG	0x7e20009c:RW
GPPUDCLK2_REG	0x7e2000a0:RW
GPPUD_REG	0x7e200094:RW
GPREN0_REG	0x7e20004c:RW
GPREN1_REG	0x7e200050:RW
GPREN2_REG	0x7e200054:RW
GPSET0_REG	0x7e20001c:RW
GPSET1_REG	0x7e200020:RW
GPSET2_REG	0x7e200024:RW
GRDAADR0_REG	0x1a005a40:RW
GRDAADR1_REG	0x1a005a44:RW
GRDAADR2_REG	0x1a005a48:RW
GRDAADR3_REG	0x1a005a4c:RW
GRDAADR4_REG	0x1a005a50:RW
GRDAADR5_REG	0x1a005a54:RW
GRDAADR6_REG	0x1a005a58:RW
GRDAADR7_REG	0x1a005a5c:RW
GRDACFG0_REG	0x1a005a20:RW
GRDACFG1_REG	0x1a005a24:RW
GRDACFG2_REG	0x1a005a28:RW
GRDACFG3_REG	0x1a005a2c:RW
GRDACFG4_REG	0x1a005a30:RW
GRDACFG5_REG	0x1a005a34:RW
GRDACFG6_REG	0x1a005a38:RW
GRDACFG7_REG	0x1a005a3c:RW
GRDCFG_REG	0x1a005a04:RW
GRDCS_REG	0x1a005a00:RW
GRFCBA_REG	0x1a005414:RW
GRFCCFG_REG	0x1a005410:RW
GRFCCV0_REG	0x1a005440:RW
GRFCCV1_REG	0x1a005444:RW
GRFCCV2_REG	0x1a005448:RW
GRFCCV3_REG	0x1a00544c:RW
GRFCCV4_REG	0x1a005450:RW
GRFCCV5_REG	0x1a005454:RW
GRFCCV6_REG	0x1a005458:RW
GRFCCV7_REG	0x1a00545c:RW
GRFCFG_REG	0x1a005404:RW
GRFCMSK_REG	0x1a00542c:RW
GRFCSTAT_REG	0x1a005500:RW
GRFCS_REG	0x1a005400:RW
GRFDIMS_REG	0x1a00540c:RW
GRFEBA_REG	0x1a005434:RW
GRFECFG_REG	0x1a005430:RW
GRFSCV_REG	0x1a005428:RW
GRFTLOC_REG	0x1a005408:RW
GRFZBA_REG	0x1a005420:RW
GRFZCFG_REG	0x1a00541c:RW
GRFZCV_REG	0x1a005424:RW
GRMCCT_REG	0x1a005c28:RW
GRMCFG_REG	0x1a005c04:RW
GRMCIH0_REG	0x1a005cc0:RW
GRMCIH1_REG	0x1a005ce0:RW
GRMCIL0_REG	0x1a005c80:RW
GRMCIL1_REG	0x1a005ca0:RW
GRMCS_REG	0x1a005c00:RW
GRMMCT_REG	0x1a005c1c:RW
GRMOADR_REG	0x1a005c14:RW
GRMOCT_REG	0x1a005c18:RW
GRMSADR_REG	0x1a005c0c:RW
GRMSCT_REG	0x1a005c10:RW
GRMSSI0_REG	0x1a005c20:RW
GRMSSI1_REG	0x1a005c24:RW
GRMSVI_REG	0x1a005c08:RW
GROCFG_REG	0x1a005004:RW
GROCS_REG	0x1A005000:RW
GRODBGA_REG	0x1a005100:RW
GROIDC_REG	0x1a005008:RW
GROPCTR0_REG	0x1a005180:RW
GROPCTR10_REG	0x1a0051d0:RW
GROPCTR11_REG	0x1a0051d8:RW
GROPCTR1_REG	0x1a005188:RW
GROPCTR2_REG	0x1a005190:RW
GROPCTR3_REG	0x1a005198:RW
GROPCTR4_REG	0x1a0051a0:RW
GROPCTR5_REG	0x1a0051a8:RW
GROPCTR6_REG	0x1a0051b0:RW
GROPCTR7_REG	0x1a0051b8:RW
GROPCTR8_REG	0x1a0051c0:RW
GROPCTR9_REG	0x1a0051c8:RW
GROPCTRC_REG	0x1a005170:RW
GROPCTRE_REG	0x1a005174:RW
GROPCTRS0_REG	0x1a005184:RW
GROPCTRS10_REG	0x1a0051d4:RW
GROPCTRS11_REG	0x1a0051dc:RW
GROPCTRS1_REG	0x1a00518c:RW
GROPCTRS2_REG	0x1a005194:RW
GROPCTRS3_REG	0x1a00519c:RW
GROPCTRS4_REG	0x1a0051a4:RW
GROPCTRS5_REG	0x1a0051ac:RW
GROPCTRS6_REG	0x1a0051b4:RW
GROPCTRS7_REG	0x1a0051bc:RW
GROPCTRS8_REG	0x1a0051c4:RW
GROPCTRS9_REG	0x1a0051cc:RW
GROPCTR_FBC_CZ_CLRFLG_FETCHES	0x22
GROPCTR_FBC_CZ_EVICTIONS	0x31
GROPCTR_FBC_CZ_FETCHES	0x30
GROPCTR_FBC_CZ_FETCH_STALLS	0x28
GROPCTR_FBC_CZ_FE_DISCARDED	0x2E
GROPCTR_FBC_CZ_FE_HITS	0x2D
GROPCTR_FBC_CZ_FE_LINE_REQS	0x2A
GROPCTR_FBC_CZ_FE_MISSES	0x2C
GROPCTR_FBC_CZ_FE_QUAD_REQS	0x29
GROPCTR_FBC_CZ_FE_UNUSED	0x2B
GROPCTR_FBC_CZ_LINE_FLUSHES	0x23
GROPCTR_FBC_CZ_PBE_HITS	0x27
GROPCTR_FBC_CZ_PBE_MISSES	0x26
GROPCTR_FBC_CZ_PBE_REQS	0x24
GROPCTR_FBC_CZ_PBE_STALLS	0x25
GROPCTR_FBC_CZ_UM_STALLS	0x2F
GROPCTR_FBC_EZ_CLRFLG_FETCHES	0x32
GROPCTR_FBC_EZ_EVICTIONS	0x3F
GROPCTR_FBC_EZ_FETCHES	0x3E
GROPCTR_FBC_EZ_FETCH_STALLS	0x38
GROPCTR_FBC_EZ_FE_FETCHES	0x3C
GROPCTR_FBC_EZ_FE_HITS	0x3B
GROPCTR_FBC_EZ_FE_MISSES	0x3A
GROPCTR_FBC_EZ_FE_REQS	0x39
GROPCTR_FBC_EZ_LINE_FLUSHES	0x33
GROPCTR_FBC_EZ_PBE_HITS	0x37
GROPCTR_FBC_EZ_PBE_MISSES	0x36
GROPCTR_FBC_EZ_PBE_REQS	0x34
GROPCTR_FBC_EZ_PBE_STALLS	0x35
GROPCTR_FBC_EZ_UM_STALLS	0x3D
GROPCTR_FEINVALIDPIXELS	0x08
GROPCTR_FEPEZIDLE	0x0A
GROPCTR_FEPEZRDY	0x09
GROPCTR_FESPMRDY	0x0C
GROPCTR_FESPMSTALL	0x0D
GROPCTR_FESTALLPREFETCH	0x0B
GROPCTR_FEVALIDPRIMS	0x05
GROPCTR_FEVALIDQUADS	0x07
GROPCTR_FEZCULLEDQUADS	0x06
GROPCTR_FOVCLIPPEDPRIMS	0x02
GROPCTR_FOVCULLEDPRIMS	0x01
GROPCTR_NOFEPIXELPRIMS	0x04
GROPCTR_PBE_DEPTH_TEST_FAIL	0x1F
GROPCTR_PBE_DPTH_STCL_PASS	0x21
GROPCTR_PBE_FE_STALLS	0x1E
GROPCTR_PBE_STCL_TEST_FAIL	0x20
GROPCTR_REVCULLEDPRIMS	0x03
GROPCTR_TU0_AXI_REQ_FIFO_FULL	0x10
GROPCTR_TU0_CACHE_ACCESSES	0x11
GROPCTR_TU0_CACHE_MISSES	0x14
GROPCTR_TU0_CACHE_RCV_WAITS	0x15
GROPCTR_TU0_CACHE_REQ_STALLS	0x13
GROPCTR_TU0_CACHE_STALLS	0x12
GROPCTR_TU0_SAME_BANK_STALL	0x0F
GROPCTR_TU0_SAME_SET_STALL	0x0E
GROPCTR_TU1_AXI_REQ_FIFO_FULL	0x18
GROPCTR_TU1_CACHE_ACCESSES	0x19
GROPCTR_TU1_CACHE_MISSES	0x1C
GROPCTR_TU1_CACHE_RCV_WAITS	0x1D
GROPCTR_TU1_CACHE_REQ_STALLS	0x1B
GROPCTR_TU1_CACHE_STALLS	0x1A
GROPCTR_TU1_SAME_BANK_STALL	0x17
GROPCTR_TU1_SAME_SET_STALL	0x16
GRPABS_REG	0x1a005660:RW
GRPBCC_REG	0x1a005654:RW
GRPBCFG_REG	0x1a005650:RW
GRPCBS_REG	0x1a00565c:RW
GRPCDSM_REG	0x1a005658:RW
GRPCFG_REG	0x1a005604:RW
GRPCLSZ_REG	0x1a00560c:RW
GRPCLXY_REG	0x1a005608:RW
GRPCS_REG	0x1a005600:RW
GRPCZSM_REG	0x1a005658:RW
GRPFCOL_REG	0x1a005664:RW
GRPSBCG_REG	0x1a005648:RW
GRPSCC_REG	0x1a00564c:RW
GRPSFCG_REG	0x1a005644:RW
GRPVORG_REG	0x1a005610:RW
GRPZBCG_REG	0x1a005640:RW
GRP_FDBGB_REG	0x1a005744:RW
GRP_FDBGO_REG	0x1a005740:RW
GRP_FDBGR_REG	0x1a005748:RW
GRP_FDBGS_REG	0x1a00574c:RW
GRP_SDBG0_REG	0x1a005750:RW
GRSAADR_REG	0x1a00581c:RW
GRSACT_REG	0x1a005820:RW
GRSCFG_REG	0x1a005804:RW
GRSCS_REG	0x1a005800:RW
GRSDMAX_REG	0x1a005830:RW
GRSDMIN_REG	0x1a00582c:RW
GRSDOF_REG	0x1a005824:RW
GRSDOU_REG	0x1a005828:RW
GRSDZS_REG	0x1a005840:RW
GRSFSF_REG	0x1a00583c:RW
GRSHPX_REG	0x1a005844:RW
GRSLW_REG	0x1a005838:RW
GRSPADR_REG	0x1a005814:RW
GRSPCT_REG	0x1a005818:RW
GRSPSZ_REG	0x1a005834:RW
GRSSP_REG	0x1a005810:RW
GRSVADR_REG	0x1a005808:RW
GRSVFMT_REG	0x1a00580c:RW
GRS_DBGE_REG	0x1a005900:RW
GRTBCOL0_REG	0x1a00520c:RW
GRTBCOL1_REG	0x1a00522c:RW
GRTBCOL2_REG	0x1a00524c:RW
GRTBCOL3_REG	0x1a00526c:RW
GRTBCOL4_REG	0x1a00528c:RW
GRTBCOL5_REG	0x1a0052ac:RW
GRTBCOL6_REG	0x1a0052cc:RW
GRTBCOL7_REG	0x1a0052ec:RW
GRTCDIM0_REG	0x1a005308:RW
GRTCDIM1_REG	0x1a005388:RW
GRTCFG0_REG	0x1a005204:RW
GRTCFG1_REG	0x1a005224:RW
GRTCFG2_REG	0x1a005244:RW
GRTCFG3_REG	0x1a005264:RW
GRTCFG4_REG	0x1a005284:RW
GRTCFG5_REG	0x1a0052a4:RW
GRTCFG6_REG	0x1a0052c4:RW
GRTCFG7_REG	0x1a0052e4:RW
GRTCOFF0_REG	0x1a005304:RW
GRTCOFF1_REG	0x1a005384:RW
GRTCS0_REG	0x1a005200:RW
GRTCS1_REG	0x1a005280:RW
GRTDBG0_REG	0x1a005300:RW
GRTDIM0_REG	0x1a005208:RW
GRTDIM1_REG	0x1a005228:RW
GRTDIM2_REG	0x1a005248:RW
GRTDIM3_REG	0x1a005268:RW
GRTDIM4_REG	0x1a005288:RW
GRTDIM5_REG	0x1a0052a8:RW
GRTDIM6_REG	0x1a0052c8:RW
GRTDIM7_REG	0x1a0052e8:RW
GRTLBIAS0_REG	0x1a00521c:RW
GRTLBIAS1_REG	0x1a00523c:RW
GRTLBIAS2_REG	0x1a00525c:RW
GRTLBIAS3_REG	0x1a00527c:RW
GRTLBIAS4_REG	0x1a00529c:RW
GRTLBIAS5_REG	0x1a0052bc:RW
GRTLBIAS6_REG	0x1a0052dc:RW
GRTLBIAS7_REG	0x1a0052fc:RW
GRTMPM0_BASE	0x1A005E00
GRTMPM0_REG	0x1a005e00:RW
GRTMPM1_BASE	0x1A005F00
GRTMPM1_REG	0x1a005f00:RW
GRTMPM_MASK	0xFFFFFF00
GRTPTBA0_REG	0x1a005220:RW
GRTPTBA1_REG	0x1a0052a0:RW
GRVVSTRD_REG	0x1a005d00:RW
GR_FBC_ADDR_MASK	0x0000007F
GR_FBC_BASE	0x1A005400
GR_FBC_DEBUG_ADDR_MASK	0x7F
GR_FBC_DEBUG_BASE	0x1A005500
GR_PPL_ADDR_MASK	0x0000007F
GR_PPL_BASE	0x1A005600
GR_PPL_DEBUG_ADDR_MASK	0x0000001F
GR_PPL_DEBUG_BASE	0x1A005740
GR_PSE_ADDR_MASK	0x0000007f
GR_PSE_BASE	0x1A005800
GR_PSE_DEBUG_ADDR_MASK	0x00000003
GR_PSE_DEBUG_BASE	0x1A005900
GR_SYSTEM_BASE	0x1A005000
GR_SYSTEM_DEBUG_BASE	0x1A005100
GR_TU_ADDR_MASK	0x000000FF
GR_TU_BASE0	0x1A005200
GR_TU_BASE1	0x1A005220
GR_TU_BASE2	0x1A005240
GR_TU_BASE3	0x1A005260
GR_TU_BASE4	0x1A005280
GR_TU_BASE5	0x1A0052A0
GR_TU_BASE6	0x1A0052C0
GR_TU_BASE7	0x1A0052E0
GR_TU_DBG_BASE	0x1A005300
GR_TU_UNIT_MASK	0xFFFFFF1F
GR_UNIFORM_ADDR_MASK	0x00000fff
GR_UNIFORM_BASE	0x1a00c000
GR_UNIFORM_SIZE	0x00001000
GR_VCACHE_ADDR_MASK	0x00001fff
GR_VCACHE_BASE	0x1a00a000
GR_VCACHE_SIZE	0x00002000
GR_VCD_ADDR_MASK	0x0000007f
GR_VCD_BASE	0x1A005A00
GR_VCM_ADDR_MASK	0x0000003f
GR_VCM_BASE	0x1A005C00
GR_VCM_CI_ADDR_MASK	0x0000007f
GR_VCM_CI_BASE	0x1A005C80
GR_VPM_VRFCFG_ADDR_MASK	0x00000003
GR_VPM_VRFCFG_BASE	0x1A005D00
HW_POINTER_TO_ADDRESS(pointer)	MACRO
HW_REGISTER_RO(addr)	MACRO
HW_REGISTER_RW(addr)	MACRO
I1CACHE_BASE_REG	0xffffffff:RW
I2CA_0_REG	0x7e20500c:RW
I2CA_1_REG	0x7e80400c:RW
I2CA_2_REG	0x7e80500c:RW
I2CA_3_REG	I2C_BASE_3 + 0x0C:RW
I2CA_REG	0x7e20500c:RW
I2CA_x(x)	MACRO
I2CCLKT_0_REG	0x7e20501c:RW
I2CCLKT_1_REG	0x7e80401c:RW
I2CCLKT_2_REG	0x7e80501c:RW
I2CCLKT_3_REG	I2C_BASE_3 + 0x1C:RW
I2CCLKT_REG	0x7e20501c:RW
I2CCLKT_x(x)	MACRO
I2CC_0_REG	0x7e205000:RW
I2CC_1_REG	0x7e804000:RW
I2CC_2_REG	0x7e805000:RW
I2CC_3_REG	I2C_BASE_3 + 0x00:RW
I2CC_CLEAR	48
I2CC_EN	0x8000
I2CC_INTD	256
I2CC_INTR	0x400
I2CC_INTT	0x200
I2CC_READ	1
I2CC_REG	0x7e205000:RW
I2CC_START	128
I2CC_x(x)	MACRO
I2CDEL_0_REG	0x7e205018:RW
I2CDEL_1_REG	0x7e804018:RW
I2CDEL_2_REG	0x7e805018:RW
I2CDEL_3_REG	I2C_BASE_3 + 0x18:RW
I2CDEL_FEDL	(16)
I2CDEL_REDL	(0)
I2CDEL_REG	0x7e205018:RW
I2CDEL_x(x)	MACRO
I2CDIV_0_REG	0x7e205014:RW
I2CDIV_1_REG	0x7e804014:RW
I2CDIV_2_REG	0x7e805014:RW
I2CDIV_3_REG	I2C_BASE_3 + 0x14:RW
I2CDIV_REG	0x7e205014:RW
I2CDIV_x(x)	MACRO
I2CDLEN_0_REG	0x7e205008:RW
I2CDLEN_1_REG	0x7e804008:RW
I2CDLEN_2_REG	0x7e805008:RW
I2CDLEN_3_REG	I2C_BASE_3 + 0x08:RW
I2CDLEN_REG	0x7e205008:RW
I2CDLEN_x(x)	MACRO
I2CFIFO_0_REG	0x7e205010:RW
I2CFIFO_1_REG	0x7e804010:RW
I2CFIFO_2_REG	0x7e805010:RW
I2CFIFO_3_REG	I2C_BASE_3 + 0x10:RW
I2CFIFO_REG	0x7e205010:RW
I2CFIFO_x(x)	MACRO
I2CS_0_REG	0x7e205004:RW
I2CS_1_REG	0x7e804004:RW
I2CS_2_REG	0x7e805004:RW
I2CS_3_REG	I2C_BASE_3 + 0x04:RW
I2CS_CLKT	0x200
I2CS_DONE	2
I2CS_ERR	256
I2CS_REG	0x7e205004:RW
I2CS_RXD	32
I2CS_RXF	128
I2CS_RXR	8
I2CS_TA	1
I2CS_TXD	16
I2CS_TXE	64
I2CS_TXW	4
I2CS_x(x)	MACRO
I2C_BASE_0	0x7e205000
I2C_BASE_1	0x7e804000
I2C_BASE_2	0x7e805000
IC0CS_REG	0x7ee02000:RW
IC1CS_REG	0xffffffff:RW
IC1END_REG	0xffffffff:RW
IC1START_REG	0xffffffff:RW
IC_0_REG	0x7e002000:RW
IC_1_REG	0xffffffff:RW
IC_MASK0_REG	0x7e002010:RW
IC_REG	0x7e002000:RW
IC_VADDR_REG	0x7e002030:RW
IDCCFG_REG	0x10002014:RW
IDCCMD_REG	0x10002010:RW
IDCKEYHU_REG	0x10002008:RW
IDCKEYLU_REG	0x1000200C:RW
IDCKSEL_REG	0x10002018:RW
IDCLVWMCU_REG	0x10002000:RW
IDCLVWMC_REG	0x10002020:RW
IDCMDIDU_REG	0x10002004:RW
IDCMDID_REG	0x10002024:RW
IFORCE0_0_REG	0x7e002040:RW
IFORCE0_1_REG	0xffffffff:RW
IFORCE1_0_REG	0x7e002044:RW
IFORCE1_1_REG	0xffffffff:RW
IMASK0_0_REG	0x7e002010:RW
IMASK0_1_REG	0xffffffff:RW
IMASK0_REG	0x7e002010:RW
IMASK1_0_REG	0x7e002014:RW
IMASK1_1_REG	0xffffffff:RW
IMASK1_REG	0x7e002014:RW
IMASK2_0_REG	0x7e002018:RW
IMASK2_1_REG	0xffffffff:RW
IMASK2_REG	0x7e002018:RW
IMASK3_0_REG	0x7e00201c:RW
IMASK3_1_REG	0xffffffff:RW
IMASK3_REG	0x7e00201c:RW
IMASK4_0_REG	0x7e002020:RW
IMASK4_1_REG	0xffffffff:RW
IMASK5_0_REG	0x7e002024:RW
IMASK5_1_REG	0xffffffff:RW
IMASK6_0_REG	0x7e002028:RW
IMASK6_1_REG	0xffffffff:RW
IMASK7_0_REG	0x7e00202c:RW
IMASK7_1_REG	0xffffffff:RW
IMASKx_0(x)	MACRO
IMASKx_1(x)	MACRO
INTERRUPT_3D	74
INTERRUPT_ADC	122
INTERRUPT_ARM	94
INTERRUPT_ASDIO	126
INTERRUPT_AUXIO	93
INTERRUPT_AVE	101
INTERRUPT_AVSPMON	127
INTERRUPT_CAM0	102
INTERRUPT_CAM1	103
INTERRUPT_CCP2	102
INTERRUPT_CCP2TX	98
INTERRUPT_CDP	110
INTERRUPT_CODEC0	68
INTERRUPT_CODEC1	69
INTERRUPT_CODEC2	70
INTERRUPT_CPG	124
INTERRUPT_CPR	111
INTERRUPT_CRYPTO	98
INTERRUPT_CSI2	103
INTERRUPT_DMA0	80
INTERRUPT_DMA1	81
INTERRUPT_DMA10	90
INTERRUPT_DMA11	91
INTERRUPT_DMA11_12_13_14	91
INTERRUPT_DMA12	92
INTERRUPT_DMA13	93
INTERRUPT_DMA14	94
INTERRUPT_DMA15	95
INTERRUPT_DMA2	82
INTERRUPT_DMA3	83
INTERRUPT_DMA4	84
INTERRUPT_DMA5	85
INTERRUPT_DMA6	86
INTERRUPT_DMA7	87
INTERRUPT_DMA8	88
INTERRUPT_DMA9	89
INTERRUPT_DMA_ALL	92
INTERRUPT_DMA_VPU	95
INTERRUPT_DSI0	100
INTERRUPT_DSI1	108
INTERRUPT_DUMMY	127
INTERRUPT_EXCEPTION_NUM	32
INTERRUPT_EXCEPTION_OFFSET	0
INTERRUPT_GPIO0	112
INTERRUPT_GPIO1	113
INTERRUPT_GPIO2	114
INTERRUPT_GPIO3	116
INTERRUPT_GPION	115
INTERRUPT_HARDINT_NUM	64
INTERRUPT_HARDINT_OFFSET	64
INTERRUPT_HDMI0	104
INTERRUPT_HDMI1	105
INTERRUPT_HOSTINTERFACE	96
INTERRUPT_HOSTPORT	96
INTERRUPT_HW_NUM	(64)
INTERRUPT_HW_OFFSET	(64)
INTERRUPT_I2C	117
INTERRUPT_I2C_SLV	107
INTERRUPT_I2SPCM	119
INTERRUPT_ISP	72
INTERRUPT_JPEG	71
INTERRUPT_MULTICORESYNC0	76
INTERRUPT_MULTICORESYNC1	77
INTERRUPT_MULTICORESYNC2	78
INTERRUPT_MULTICORESYNC3	79
INTERRUPT_PARALLELCAMERA	107
INTERRUPT_PIXELVALVE0	108
INTERRUPT_PIXELVALVE1	106
INTERRUPT_PLL	109
INTERRUPT_PWA0	109
INTERRUPT_PWA1	110
INTERRUPT_RNG	125
INTERRUPT_SDC	99
INTERRUPT_SDCARDHOST	120
INTERRUPT_SDIO	120
INTERRUPT_SLIMBUS	116
INTERRUPT_SMI	111
INTERRUPT_SOFTINT_NUM	32
INTERRUPT_SOFTINT_OFFSET	32
INTERRUPT_SPARE1	99
INTERRUPT_SPARE2	124
INTERRUPT_SPARE3	125
INTERRUPT_SPARE4	126
INTERRUPT_SPARE5	127
INTERRUPT_SPI	118
INTERRUPT_SW_NUM	(32)
INTERRUPT_SW_OFFSET	(32)
INTERRUPT_TIMER0	64
INTERRUPT_TIMER1	65
INTERRUPT_TIMER2	66
INTERRUPT_TIMER3	67
INTERRUPT_TRANSPOSER	75
INTERRUPT_UART	121
INTERRUPT_UART_SPI0_SPI1	93
INTERRUPT_USB	73
INTERRUPT_VEC	123
INTERRUPT_VECTOR_BASE	0
INTERRUPT_VIDEOSCALER	97
INT_CTL_BASE_ADDR1_REG	0xffffffff:RW
IPROFILE_0_REG	0x7e002038:RW
IPROFILE_1_REG	0xffffffff:RW
ISRC0_0_REG	0x7e002008:RO
ISRC0_1_REG	0xffffffff:RW
ISRC1_0_REG	0x7e00200c:RO
ISRC1_1_REG	0xffffffff:RW
ISRC_REG	0x7e002008:RO
IS_0_REG	0x7e002004:RO
IS_1_REG	0xffffffff:RW
IS_ALIAS_COHERENT(x)	MACRO
IS_ALIAS_DIRECT(x)	MACRO
IS_ALIAS_L1L2_NONALLOCATING(x)	MACRO
IS_ALIAS_L1_NONALLOCATING(x)	MACRO
IS_ALIAS_NONALLOCATING(x)	MACRO
IS_ALIAS_NORMAL(x)	MACRO
IS_ALIAS_NOT_L1(p)	MACRO
IS_ALIAS_PERIPHERAL(x)	MACRO
IS_ALIAS_STREAMING(x)	MACRO
IS_REG	0x7e002004:RO
IVADDR_0_REG	0x7e002030:RW
IVADDR_1_REG	0xffffffff:RW
IWAKEUP_0_REG	0x7e002034:RW
IWAKEUP_1_REG	0xffffffff:RW
JC0BA_REG	0x7e00504c:RW
JC0S_REG	0x7e005058:RW
JC0W_REG	0x7e005064:RW
JC1BA_REG	0x7e005050:RW
JC1S_REG	0x7e00505c:RW
JC1W_REG	0x7e005068:RW
JC2BA_REG	0x7e005054:RW
JC2S_REG	0x7e005060:RW
JC2W_REG	0x7e00506c:RW
JCBA_REG	0x7e005010:RW
JCTRL_DCTEN	16
JCTRL_FLUSH	4
JCTRL_MODE	1
JCTRL_REG	0x7e005000:RW
JCTRL_RESET	8
JCTRL_START	128
JCTRL_STUFF	2
JDCCTRL_DCCOMP_MASK	0xFFFF
JDCCTRL_DISDC	0x100000
JDCCTRL_REG	0x7e00500c:RW
JDCCTRL_SETDC(n)	MACRO
JHADDR_REG	0x7e005028:RW
JHADDR_TABLEF	0x80000000
JHWDATA_REG	0x7e00502c:RW
JICST_CDONE	0x10000
JICST_ERR	0x80000
JICST_INTCD	1
JICST_INTE	8
JICST_INTM	4
JICST_INTSD	2
JICST_MARKER	0x40000
JICST_REG	0x7e005004:RW
JICST_SDONE	0x20000
JMADDR_REG	0x7e005030:RW
JMCTRL_420_MODE	0
JMCTRL_422_MODE	0x4000
JMCTRL_444_MODE	0x8000
JMCTRL_AC_TAB(n)	MACRO
JMCTRL_CMP(n)	MACRO
JMCTRL_DC_TAB(n)	MACRO
JMCTRL_NUMCMP	256
JMCTRL_REG	0x7e005008:RW
JMCTRL_UNUSED_BITS	0xf800
JMOP_REG	0x7e005024:RW
JMWDATA_REG	0x7e005034:RW
JNCB_REG	0x7e005014:RW
JNSB_REG	0x7e00501c:RW
JOADDR_REG	0x7e005038:RW
JOWDATA_REG	0x7e00503c:RW
JQADDR_REG	0x7e005040:RW
JQCTRL_REG	0x7e005048:RW
JQWDATA_REG	0x7e005044:RW
JSBO_REG	0x7e005020:RW
JSDA_REG	0x7e005018:RW
L2CACHE_SIZE	(1024 * 128)
L2CS_REG	0x7ee01000:RW
L2END_REG	0x7ee01008:RW
L2START_REG	0x7ee01004:RW
MAX_DMA_NUM	8
MAX_DMA_SUB	1
MAX_EXCEPTION_NUM	8
MAX_GPIO_NUM	2
MAX_TIMER_NUM	4
MULTICORE_SYNC_ICCLR_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x98:RW
MULTICORE_SYNC_ICCLR_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x9C:RW
MULTICORE_SYNC_ICSET_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x90:RW
MULTICORE_SYNC_ICSET_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x94:RW
MULTICORE_SYNC_IREQ_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x84:RW
MULTICORE_SYNC_IREQ_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x88:RW
MULTICORE_SYNC_MBOX_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xA0:RW
MULTICORE_SYNC_MBOX_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xA4:RW
MULTICORE_SYNC_MBOX_2_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xA8:RW
MULTICORE_SYNC_MBOX_3_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xAC:RW
MULTICORE_SYNC_MBOX_4_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xB0:RW
MULTICORE_SYNC_MBOX_5_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xB4:RW
MULTICORE_SYNC_MBOX_6_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xB8:RW
MULTICORE_SYNC_MBOX_7_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xBC:RW
MULTICORE_SYNC_MBOX_MASK(num)	MACRO
MULTICORE_SYNC_NUM_SEMAPHORES	(32)
MULTICORE_SYNC_SEMA_MASK(num)	MACRO
MULTICORE_SYNC_SEMA_MASK_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x00:RW
MULTICORE_SYNC_SEMA_MASK_10_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x28:RW
MULTICORE_SYNC_SEMA_MASK_11_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x2C:RW
MULTICORE_SYNC_SEMA_MASK_12_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x30:RW
MULTICORE_SYNC_SEMA_MASK_13_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x34:RW
MULTICORE_SYNC_SEMA_MASK_14_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x38:RW
MULTICORE_SYNC_SEMA_MASK_15_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x3C:RW
MULTICORE_SYNC_SEMA_MASK_16_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x40:RW
MULTICORE_SYNC_SEMA_MASK_17_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x44:RW
MULTICORE_SYNC_SEMA_MASK_18_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x48:RW
MULTICORE_SYNC_SEMA_MASK_19_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x4C:RW
MULTICORE_SYNC_SEMA_MASK_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x04:RW
MULTICORE_SYNC_SEMA_MASK_20_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x50:RW
MULTICORE_SYNC_SEMA_MASK_21_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x54:RW
MULTICORE_SYNC_SEMA_MASK_22_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x58:RW
MULTICORE_SYNC_SEMA_MASK_23_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x5C:RW
MULTICORE_SYNC_SEMA_MASK_24_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x60:RW
MULTICORE_SYNC_SEMA_MASK_25_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x64:RW
MULTICORE_SYNC_SEMA_MASK_26_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x68:RW
MULTICORE_SYNC_SEMA_MASK_27_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x6C:RW
MULTICORE_SYNC_SEMA_MASK_28_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x70:RW
MULTICORE_SYNC_SEMA_MASK_29_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x74:RW
MULTICORE_SYNC_SEMA_MASK_2_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x08:RW
MULTICORE_SYNC_SEMA_MASK_30_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x78:RW
MULTICORE_SYNC_SEMA_MASK_31_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x7C:RW
MULTICORE_SYNC_SEMA_MASK_3_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x0C:RW
MULTICORE_SYNC_SEMA_MASK_4_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x10:RW
MULTICORE_SYNC_SEMA_MASK_5_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x14:RW
MULTICORE_SYNC_SEMA_MASK_6_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x18:RW
MULTICORE_SYNC_SEMA_MASK_7_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x1C:RW
MULTICORE_SYNC_SEMA_MASK_8_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x20:RW
MULTICORE_SYNC_SEMA_MASK_9_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x24:RW
MULTICORE_SYNC_SEMA_STATUS_REG	MULTICORE_SYNC_BASE_ADDRESS + 0x80:RW
MULTICORE_SYNC_VPU_SEMA_0_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xC0:RW
MULTICORE_SYNC_VPU_SEMA_1_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xC4:RW
MULTICORE_SYNC_VPU_SEMA_STATUS_REG	MULTICORE_SYNC_BASE_ADDRESS + 0xC8:RW
MULTICORE_SYNC_VPU_SEMA_x(x)	MACRO
NIOREQ_REG	0x7e008000:RW
NOWNT_REG	0x7e008004:RW
PCMCS_DMAEN	0x200
PCMCS_EN	1
PCMCS_INTE	0x1000
PCMCS_INTR	0x800
PCMCS_INTT	0x400
PCMCS_REG	PCM_BASE_ADDRESS + 0x00:RW
PCMCS_RXCLR	16
PCMCS_RXD	0x100000
PCMCS_RXERR	0x10000
PCMCS_RXF	0x400000
PCMCS_RXON	2
PCMCS_RXR	0x40000
PCMCS_RXSEX	0x800000
PCMCS_RXSYNC	0x4000
PCMCS_RXTHR_1_QUARTER	128
PCMCS_RXTHR_3_QUARTER	256
PCMCS_RXTHR_EMPTY	0
PCMCS_RXTHR_FULL	0x180
PCMCS_RXTHR_LSB	7
PCMCS_SYNC	0x1000000
PCMCS_TXCLR	8
PCMCS_TXD	0x80000
PCMCS_TXE	0x200000
PCMCS_TXERR	0x8000
PCMCS_TXON	4
PCMCS_TXSYNC	0x2000
PCMCS_TXTHR_1_QUARTER	32
PCMCS_TXTHR_3_QUARTER	64
PCMCS_TXTHR_EMPTY	0
PCMCS_TXTHR_FULL	96
PCMCS_TXTHR_LSB	5
PCMCS_TXW	0x20000
PCMDREQ_REG	PCM_BASE_ADDRESS + 0x14:RW
PCMDREQ_RXDREQTHR_LSB	0
PCMDREQ_RXPANICTHR_LSB	16
PCMDREQ_TXDREQTHR_LSB	8
PCMDREQ_TXPANICTHR_LSB	24
PCMFIFO_REG	PCM_BASE_ADDRESS + 0x04:RW
PCMINTEN_REG	0x7e203018:RW
PCMINTSTC_REG	0x7e20301c:RW
PCMMODE_CLKI	0x400000
PCMMODE_CLKM	0x800000
PCMMODE_FLEN	10
PCMMODE_FRXP	0x2000000
PCMMODE_FSI	0x100000
PCMMODE_FSLEN	0
PCMMODE_FSM	0x200000
PCMMODE_FTXP	0x1000000
PCMMODE_PDMRX	0x4000000
PCMMODE_PDMRXN	0x8000000
PCMMODE_REG	PCM_BASE_ADDRESS + 0x08:RW
PCMRXC_REG	PCM_BASE_ADDRESS + 0x0C:RW
PCMTXC_REG	PCM_BASE_ADDRESS + 0x10:RW
PERFMON_BASE_ADDRESS	0x7e20d000
PIXELVALVE_0_BASE_ADDRESS	0x7e206000
PIXELVALVE_1_BASE_ADDRESS	0x7e207000
PIXELVALVE_2_BASE_ADDRESS	0x7e807000
PIXELVALVE_C_0_REG	0x7e206000:RW
PIXELVALVE_C_1_REG	0x7e207000:RW
PIXELVALVE_C_x(x)	MACRO
PIXELVALVE_HSYNC_0	PIXELVALVE0_HSYNC
PIXELVALVE_HSYNC_1	PIXELVALVE1_HSYNC
PIXELVALVE_HSYNC_x(x)	MACRO
PIXELVALVE_INTEN_0_REG	0x7e206024:RW
PIXELVALVE_INTEN_1_REG	0x7e207024:RW
PIXELVALVE_INTEN_x(x)	MACRO
PIXELVALVE_INTSTAT_0_REG	0x7e206028:RW
PIXELVALVE_INTSTAT_1_REG	0x7e207028:RW
PIXELVALVE_INTSTAT_x(x)	MACRO
PIXELVALVE_STAT_0_REG	0x7e20602c:RW
PIXELVALVE_STAT_1_REG	0x7e20702c:RW
PIXELVALVE_STAT_x(x)	MACRO
PIXELVALVE_VC_0_REG	0x7e206004:RW
PIXELVALVE_VC_1_REG	0x7e207004:RW
PIXELVALVE_VC_x(x)	MACRO
PIXELVALVE_VSIZE_0	PIXELVALVE0_VSIZE
PIXELVALVE_VSIZE_1	PIXELVALVE1_VSIZE
PIXELVALVE_VSIZE_x(x)	MACRO
PIXELVALVE_VSYNC_0	PIXELVALVE0_VSYNC
PIXELVALVE_VSYNC_1	PIXELVALVE1_VSYNC
PIXELVALVE_VSYNC_x(x)	MACRO
POWERMAN_BASE_ADDRESS	0x7e100000
PRMCS_REG	0x7e20d000:RW
PRMCV_REG	0x7e20d004:RW
PRMSCC_REG	0x7e20d008:RW
PWMCTL_CLRF1	6
PWMCTL_MODE(n)	MACRO
PWMCTL_MODE1	1
PWMCTL_MODE2	9
PWMCTL_MODE3	17
PWMCTL_MODE4	25
PWMCTL_MSEN(n)	MACRO
PWMCTL_MSEN1	7
PWMCTL_MSEN2	15
PWMCTL_MSEN3	23
PWMCTL_MSEN4	31
PWMCTL_POLA(n)	MACRO
PWMCTL_POLA1	4
PWMCTL_POLA2	12
PWMCTL_POLA3	20
PWMCTL_POLA4	28
PWMCTL_PWEN(n)	MACRO
PWMCTL_PWEN1	0
PWMCTL_PWEN2	8
PWMCTL_PWEN3	16
PWMCTL_PWEN4	24
PWMCTL_REG	0x7e20c000:RW
PWMCTL_RPTL(n)	MACRO
PWMCTL_RPTL1	2
PWMCTL_RPTL2	10
PWMCTL_RPTL3	18
PWMCTL_RPTL4	26
PWMCTL_SBIT(n)	MACRO
PWMCTL_SBIT1	3
PWMCTL_SBIT2	11
PWMCTL_SBIT3	19
PWMCTL_SBIT4	27
PWMCTL_USEF(n)	MACRO
PWMCTL_USEF1	5
PWMCTL_USEF2	13
PWMCTL_USEF3	21
PWMCTL_USEF4	29
PWMDAT1_REG	0x7e20c014:RW
PWMDAT2_REG	0x7e20c024:RW
PWMDAT3_REG	0x7e20c034:RW
PWMDAT4_REG	0x7e20c044:RW
PWMDMAC_DREQ	0
PWMDMAC_DREQ_LEN	8
PWMDMAC_ENAB	31
PWMDMAC_PANIC	8
PWMDMAC_PANIC_LEN	8
PWMDMAC_REG	0x7e20c008:RW
PWMFIF1_REG	0x7e20c018:RW
PWMRNG1_REG	0x7e20c010:RW
PWMRNG2_REG	0x7e20c020:RW
PWMRNG3_REG	0x7e20c030:RW
PWMRNG4_REG	0x7e20c040:RW
PWMSTA_BERR	8
PWMSTA_EMPT1	1
PWMSTA_FULL1	0
PWMSTA_GAPO1	4
PWMSTA_GAPO2	5
PWMSTA_GAPO3	6
PWMSTA_GAPO4	7
PWMSTA_REG	0x7e20c004:RW
PWMSTA_RERR1	3
PWMSTA_STA1	9
PWMSTA_STA2	10
PWMSTA_STA3	11
PWMSTA_STA4	12
PWMSTA_WERR1	2
RESET_CONTROLLER_BASE	RS_BASE
RSC0ADDR_REG	RS_BASE + 0x10:RW
RSTCS_REG	RS_BASE + 0x0:RW
RSTFD_REG	RS_BASE + 0xc:RW
RSTID_REG	RS_BASE + 0x8:RW
RSTWD_REG	RS_BASE + 0x4:RW
RUN_ARBITER_CTRL_BASE_ADDRESS_REG	0xffffffff:RW
SDARG_REG	SDCARD_BASE + 0x04:RW
SDCDIV_REG	SDCARD_BASE + 0x0C:RW
SDCMD_REG	SDCARD_BASE + 0x00:RW
SDCS_REG	0x7ee00000:RW
SDCYC_REG	0x7ee00030:RO
SDDATA_REG	SDCARD_BASE + 0x40:RW
SDDAT_REG	0x7ee00038:RO
SDEDM_REG	SDCARD_BASE + 0x34:RW
SDHBCT_REG	SDCARD_BASE + 0x3C:RW
SDHBLC_REG	SDCARD_BASE + 0x50:RW
SDHCFG_REG	SDCARD_BASE + 0x38:RW
SDHSTS_REG	SDCARD_BASE + 0x20:RW
SDIDL_REG	0x7ee00018:RW
SDRAC_REG	0x7ee0002c:RO
SDRAM_BASE_ADDRESS	0x7ee00000
SDRAM_CTRL_DMA	0
SDRAM_SIZE	(1024 * 1024 * 128)
SDRAM_START_ADDRESS	0
SDRDC_REG	0x7ee00024:RO
SDRSP0_REG	SDCARD_BASE + 0x10:RW
SDRSP1_REG	SDCARD_BASE + 0x14:RW
SDRSP2_REG	SDCARD_BASE + 0x18:RW
SDRSP3_REG	SDCARD_BASE + 0x1C:RW
SDRTC_REG	0x7ee0001c:RW
SDSA_REG	0x7ee00004:RW
SDSB_REG	0x7ee00008:RW
SDSC_REG	0x7ee0000c:RW
SDSECEND0_REG	0x7ee00040:RW
SDSECEND1_REG	0x7ee00048:RW
SDSECEND2_REG	0x7ee00050:RW
SDSECEND3_REG	0x7ee00058:RW
SDSECSRT0_REG	0x7ee0003c:RW
SDSECSRT1_REG	0x7ee00044:RW
SDSECSRT2_REG	0x7ee0004c:RW
SDSECSRT3_REG	0x7ee00054:RW
SDTMC_REG	0x7ee0007c:RW
SDTOUT_REG	SDCARD_BASE + 0x08:RW
SDVDD_REG	SDCARD_BASE + 0x30:RW
SDWDC_REG	0x7ee00028:RO
SDWTC_REG	0x7ee00020:RO
SET_GPIO_ALT(g,a)	MACRO
SMIA_DEVICE	8
SMIA_REG	0x7e600008:RW
SMICS_ACTIVE	2
SMICS_AFERR	25
SMICS_CLEARFIFO	4
SMICS_DONE	1
SMICS_EDREQ	15
SMICS_ENABLE	0
SMICS_INTD	9
SMICS_INTR	11
SMICS_INTT	10
SMICS_PAD	6
SMICS_PVMODE	12
SMICS_PXLDAT	14
SMICS_REG	0x7e600000:RW
SMICS_RXD	29
SMICS_RXF	31
SMICS_RXR	27
SMICS_SETERR	13
SMICS_START	3
SMICS_TEEN	8
SMICS_TXD	28
SMICS_TXE	30
SMICS_TXW	26
SMICS_WRITE	5
SMIDA_DEVICE	8
SMIDA_REG	0x7e600038:RW
SMIDCS_DONE	2
SMIDCS_ENABLE	0
SMIDCS_REG	0x7e600034:RW
SMIDCS_START	1
SMIDCS_WRITE	3
SMIDC_DMAEN	28
SMIDC_DMAP	24
SMIDC_PANICR	18
SMIDC_PANICW	12
SMIDC_REG	0x7e600030:RW
SMIDC_REQR	6
SMIDC_REQW	0
SMIDD_REG	0x7e60003c:RW
SMIDSR0_REG	0x7e600010:RW
SMIDSR1_REG	0x7e600018:RW
SMIDSR2_REG	0x7e600020:RW
SMIDSR3_REG	0x7e600028:RW
SMIDSW0_REG	0x7e600014:RW
SMIDSW1_REG	0x7e60001c:RW
SMIDSW2_REG	0x7e600024:RW
SMIDSW3_REG	0x7e60002c:RW
SMIDS_DREQ	7
SMIDS_FORMAT	23
SMIDS_FSETUP	22
SMIDS_HOLD	16
SMIDS_MODE68	23
SMIDS_PACE	8
SMIDS_PACEALL	15
SMIDS_SETUP	24
SMIDS_STROBE	0
SMIDS_SWAP	22
SMIDS_WIDTH	30
SMID_REG	0x7e60000c:RW
SMIFD_FCNT	0
SMIFD_FLVL	8
SMIFD_REG	0x7e600040:RW
SMIL_REG	0x7e600004:RW
SPICLK_REG	SPI_BASE_ADDRESS + 0x08:RW
SPICS_REG	SPI_BASE_ADDRESS + 0x00:RW
SPIDLEN_REG	SPI_BASE_ADDRESS + 0x0C:RW
SPIFIFO_REG	SPI_BASE_ADDRESS + 0x04:RW
STC0_0_REG	0x7e00300c:RW
STC0_1_REG	0xffffffff:RW
STC0_REG	0x7e00300c:RW
STC0_x(x)	MACRO
STC1_0_REG	0x7e003010:RW
STC1_1_REG	0xffffffff:RW
STC1_REG	0x7e003010:RW
STC1_x(x)	MACRO
STC2_0_REG	0x7e003014:RW
STC2_1_REG	0xffffffff:RW
STC2_REG	0x7e003014:RW
STC2_x(x)	MACRO
STC3_0_REG	0x7e003018:RW
STC3_1_REG	0xffffffff:RW
STC3_REG	0x7e003018:RW
STC3_x(x)	MACRO
STCHI_0_REG	0x7e003008:RO
STCHI_1_REG	0xffffffff:RO
STCHI_REG	0x7e003008:RO
STCHI_x(x)	MACRO
STCLO_0_REG	0x7e003004:RO
STCLO_1_REG	0xffffffff:RO
STCLO_REG	0x7e003004:RO
STCLO_x(x)	MACRO
STCS_0_REG	0x7e003000:RW
STCS_1_REG	0xffffffff:RW
STCS_REG	0x7e003000:RW
STCS_x(x)	MACRO
STC_0_REG	0x7e003004:RO
STC_1_REG	0xffffffff:RO
STC_REG	0x7e003004:RO
STC_x(x)	MACRO
SYSTEM_TIMER_BASE1_REG	0xffffffff:RW
TE0C_REG	TECTL_BASE_ADDRESS + 0x00:RW
TE0_VSWIDTH_REG	TECTL_BASE_ADDRESS + 0x08:RW
TE1C_REG	TECTL_BASE_ADDRESS + 0x04:RW
TE1_VSWIDTH_REG	TECTL_BASE_ADDRESS + 0x0C:RW
TH0CFG_REG	0x18011004:RW
TH0CS_REG	0x18011000:RW
TH0ITPC_REG	0x1801100c:RW
TH0STPC_REG	0x18011008:RW
TH0T0PC_REG	0x18011010:RW
TH0T0UD_REG	0x18011014:RW
TH0T1PC_REG	0x18011018:RW
TH0T1UD_REG	0x1801101c:RW
TH0T2PC_REG	0x18011020:RW
TH0T2UD_REG	0x18011024:RW
TH0T3PC_REG	0x18011028:RW
TH0T3UD_REG	0x1801102c:RW
TH0_ADDR_MASK	0x0000003F
TH0_BASE	0x18011000
TH1CFG_REG	0x1a008004:RW
TH1CS_REG	0x1a008000:RW
TH1ITPC_REG	0x1a00800c:RW
TH1STPC_REG	0x1a008008:RW
TH1T0PC_REG	0x1a008010:RW
TH1T0UD_REG	0x1a008014:RW
TH1T1PC_REG	0x1a008018:RW
TH1T1UD_REG	0x1a00801c:RW
TH1T2PC_REG	0x1a008020:RW
TH1T2UD_REG	0x1a008024:RW
TH1T3PC_REG	0x1a008028:RW
TH1T3UD_REG	0x1a00802c:RW
TH1_ADDR_MASK	0x0000003F
TH1_BASE	0x1A008000
TIMER_CTRL_32BIT	2
TIMER_CTRL_DBGHALT	256
TIMER_CTRL_DIV1	0
TIMER_CTRL_DIV16	4
TIMER_CTRL_DIV256	8
TIMER_CTRL_ENABLE	128
TIMER_CTRL_ENAFREE	0x200
TIMER_CTRL_FREEDIV_MASK	0xff
TIMER_CTRL_FREEDIV_SHIFT	16)
TIMER_CTRL_IE	32
TIMER_CTRL_ONESHOT	1
TIMER_CTRL_PERIODIC	64
TRANSPOSER_BASE_ADDRESS	0x7e004000
TRANSPOSER_CONTROL_REG	0x7e00400c:RW
TRANSPOSER_DIMENSIONS_REG	0x7e004008:RW
TRANSPOSER_DST_PITCH_REG	0x7e004004:RW
TRANSPOSER_DST_PTR_REG	0x7e004000:RW
TRANSPOSER_PROGRESS_REG	0x7e004010:RO
UDLL_REG	0x7e201000:RW
UDLM_REG	0x7e201004:RW
UEN_REG	0x7e201020:RW
UFCR_REG	0x7e201008:RW
UIER_REG	0x7e201004:RW
UIIR_REG	0x7e201008:RO
ULCR_REG	0x7e20100c:RW
ULSR_REG	0x7e201014:RW
UMCR_REG	0x7e201010:RW
UMSR_REG	0x7e201018:RW
UNICAM_ANA(x)	MACRO
UNICAM_CAP0(x)	MACRO
UNICAM_CAP1(x)	MACRO
UNICAM_CLK(x)	MACRO
UNICAM_CLT(x)	MACRO
UNICAM_CMP0(x)	MACRO
UNICAM_CMP1(x)	MACRO
UNICAM_CTRL(x)	MACRO
UNICAM_DAT0(x)	MACRO
UNICAM_DAT1(x)	MACRO
UNICAM_DAT2(x)	MACRO
UNICAM_DAT3(x)	MACRO
UNICAM_DBCTL(x)	MACRO
UNICAM_DBEA0(x)	MACRO
UNICAM_DBEA1(x)	MACRO
UNICAM_DBSA0(x)	MACRO
UNICAM_DBSA1(x)	MACRO
UNICAM_DBWP(x)	MACRO
UNICAM_DCS(x)	MACRO
UNICAM_DLT(x)	MACRO
UNICAM_IBEA0(x)	MACRO
UNICAM_IBEA1(x)	MACRO
UNICAM_IBLS(x)	MACRO
UNICAM_IBSA0(x)	MACRO
UNICAM_IBSA1(x)	MACRO
UNICAM_IBWP(x)	MACRO
UNICAM_ICC(x)	MACRO
UNICAM_ICS(x)	MACRO
UNICAM_ICTL(x)	MACRO
UNICAM_IDC(x)	MACRO
UNICAM_IDCA(x)	MACRO
UNICAM_IDCD(x)	MACRO
UNICAM_IDI0(x)	MACRO
UNICAM_IDI1(x)	MACRO
UNICAM_IDPO(x)	MACRO
UNICAM_IDS(x)	MACRO
UNICAM_IHSTA(x)	MACRO
UNICAM_IHWIN(x)	MACRO
UNICAM_IPIPE(x)	MACRO
UNICAM_ISTA(x)	MACRO
UNICAM_IVSTA(x)	MACRO
UNICAM_IVWIN(x)	MACRO
UNICAM_MISC(x)	MACRO
UNICAM_PRI(x)	MACRO
UNICAM_REG(x,d)	MACRO
UNICAM_STA(x)	MACRO
UNUSED_DMA_12	0xc0000
UNUSED_DMA_14	0xe0000
URBR_REG	0x7e201000:RO
USCR_REG	0x7e20101c:RW
UTHR_REG	0x7e201000:RW
VCINTMASK0_REG	0x7f4408b8:RW
VCINTMASK1_REG	0x7f4408c0:RW
VCODEC_VERSION	821
VCSIGNAL0_REG	0x7f4408b4:RW
VCSIGNAL1_REG	0x7f4408bc:RW
VIDEOCODEC_BASE_ADDRESS	0x7f000000
VIDEOCORE_NUM_CORES	2
VIDEOCORE_NUM_GPIO_PINS	70
VIDEOCORE_NUM_UART_PORTS	1
VIDEO_ENC_PrimaryControl_REG	0x7e806068:RW
VIDEO_ENC_RevID_REG	0x7e806060:RW
VPU0_THREAD_CTRL_BASE_ADDRESS	0x18011000
VPU1_THREAD_CTRL_BASE_ADDRESS_REG	0xffffffff:RW
VPU1_UNIFORM_MEM_BASE_ADDRESS_REG	0xffffffff:RW
VRF_SIZE	0x1080
WOGLPTR_REG	0x1820FFFC:RW
WSE_CONTROL_REG	0x7e8060c4:RW
WSE_RESET_REG	0x7e8060c0:RW
WSE_VPS_CONTROL_REG	0x7e8060d0:RW
WSE_VPS_DATA_1_REG	0x7e8060cc:RW
WSE_WSS_DATA_REG	0x7e8060c8:RW

A2W

Info

description	Clock manager PLL control
base	0x7e102000
id	0x00613277
password	0x5a000000

Registers

register name	address	type	width	mask	reset
A2W_PLLA_DIG0	0x7e102000	RW	24	0x00ffffff	0000000000
A2W_PLLA_DIG1	0x7e102004	RW	24	0x00ffffff	0x00004000
A2W_PLLA_DIG2	0x7e102008	RW	24	0x00ffffff	0x00100401
A2W_PLLA_DIG3	0x7e10200c	RW	24	0x00ffffff	0x00000004
A2W_PLLA_ANA0	0x7e102010	RW	24	0x00ffffff	0000000000
A2W_PLLA_ANA1	0x7e102014	RW	24	0x00ffffff	0x001d0000
A2W_PLLA_ANA2	0x7e102018	RW	24	0x00ffffff	0000000000
A2W_PLLA_ANA3	0x7e10201c	RW	24	0x00ffffff	0x00000180
A2W_PLLC_DIG0	0x7e102020	RW	24	0x00ffffff	0000000000
A2W_PLLC_DIG1	0x7e102024	RW	24	0x00ffffff	0x00004000
A2W_PLLC_DIG2	0x7e102028	RW	24	0x00ffffff	0x00100401
A2W_PLLC_DIG3	0x7e10202c	RW	24	0x00ffffff	0x00000004
A2W_PLLC_ANA0	0x7e102030	RW	24	0x00ffffff	0000000000
A2W_PLLC_ANA1	0x7e102034	RW	24	0x00ffffff	0x001d0000
A2W_PLLC_ANA2	0x7e102038	RW	24	0x00ffffff	0000000000
A2W_PLLC_ANA3	0x7e10203c	RW	24	0x00ffffff	0x00000180
A2W_PLLD_DIG0	0x7e102040	RW	24	0x00ffffff	0000000000
A2W_PLLD_DIG1	0x7e102044	RW	24	0x00ffffff	0x00004000
A2W_PLLD_DIG2	0x7e102048	RW	24	0x00ffffff	0x00100401
A2W_PLLD_DIG3	0x7e10204c	RW	24	0x00ffffff	0x00000004
A2W_PLLD_ANA0	0x7e102050	RW	24	0x00ffffff	0000000000
A2W_PLLD_ANA1	0x7e102054	RW	24	0x00ffffff	0x001d0000
A2W_PLLD_ANA2	0x7e102058	RW	24	0x00ffffff	0000000000
A2W_PLLD_ANA3	0x7e10205c	RW	24	0x00ffffff	0x00000180
A2W_PLLH_DIG0	0x7e102060	RW	24	0x00ffffff	0000000000
A2W_PLLH_DIG1	0x7e102064	RW	24	0x00ffffff	0000000000
A2W_PLLH_DIG2	0x7e102068	RW	24	0x00ffffff	0x000000aa
A2W_PLLH_DIG3	0x7e10206c	RW	24	0x00ffffff	0000000000
A2W_PLLH_ANA0	0x7e102070	RW	24	0x00ffffff	0x00d80000
A2W_PLLH_ANA1	0x7e102074	RW	24	0x00ffffff	0x00000014
A2W_PLLH_ANA2	0x7e102078	RW	24	0x00ffffff	0000000000
A2W_PLLH_ANA3	0x7e10207c	RW	24	0x00ffffff	0000000000
A2W_HDMI_CTL0	0x7e102080	RW	24	0x00ffffff	0x00470238
A2W_HDMI_CTL1	0x7e102084	RW	24	0x00ffffff	0x00011c00
A2W_HDMI_CTL2	0x7e102088	RW	24	0x00ffffff	0x0018048e
A2W_HDMI_CTL3	0x7e10208c	RW	24	0x00ffffff	0x00000040
A2W_XOSC0	0x7e102090	RW	24	0x00ffffff	0x00820080
A2W_XOSC1	0x7e102094	RW	24	0x00ffffff	0x00000006
A2W_SMPS_CTLA0	0x7e1020a0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLA1	0x7e1020a4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLA2	0x7e1020a8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB0	0x7e1020b0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB1	0x7e1020b4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB2	0x7e1020b8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC0	0x7e1020c0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC1	0x7e1020c4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC2	0x7e1020c8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC3	0x7e1020cc	RW	24	0x00ffffff	0000000000
A2W_SMPS_LDO0	0x7e1020d0	RW	24	0x00ffffff	0000000000
A2W_SMPS_LDO1	0x7e1020d4	RW	24	0x00ffffff	0000000000
A2W_PLLB_DIG0	0x7e1020e0	RW	24	0x00ffffff	0000000000
A2W_PLLB_DIG1	0x7e1020e4	RW	24	0x00ffffff	0x00004000
A2W_PLLB_DIG2	0x7e1020e8	RW	24	0x00ffffff	0x00100401
A2W_PLLB_DIG3	0x7e1020ec	RW	24	0x00ffffff	0x00000004
A2W_PLLB_ANA0	0x7e1020f0	RW	24	0x00ffffff	0000000000
A2W_PLLB_ANA1	0x7e1020f4	RW	24	0x00ffffff	0x001d0000
A2W_PLLB_ANA2	0x7e1020f8	RW	24	0x00ffffff	0000000000
A2W_PLLB_ANA3	0x7e1020fc	RW	24	0x00ffffff	0x00000180
A2W_PLLA_CTRL	0x7e102100	RW	18	0x000373ff	0x00010000
A2W_PLLA_ANA_SSCS	0x7e102110	RW	17	0x0001ffff	0000000000
A2W_PLLC_CTRL	0x7e102120	RW	18	0x000373ff	0x00010000
A2W_PLLC_ANA_SSCS	0x7e102130	RW	17	0x0001ffff	0000000000
A2W_PLLD_CTRL	0x7e102140	RW	18	0x000373ff	0x00010000
A2W_PLLD_ANA_SSCS	0x7e102150	RW	17	0x0001ffff	0000000000
A2W_PLLH_CTRL	0x7e102160	RW	18	0x000370ff	0x00010000
A2W_HDMI_CTL_RCAL	0x7e102180	RW	17	0x00011f33	0x00010000
A2W_XOSC_CTRL	0x7e102190	RW	20	0x000ff0ff	0000000000
A2W_SMPS_A_MODE	0x7e1021a0	RW	1	0x00000001	0000000000
A2W_SMPS_B_STAT	0x7e1021b0	RW	13	0x0000111f	0000000000
A2W_SMPS_C_CLK	0x7e1021c0	RW	4	0x0000000f	0000000000
A2W_SMPS_L_SPV	0x7e1021d0	RW	5	0x0000001f	0000000000
A2W_PLLB_CTRL	0x7e1021e0	RW	18	0x000373ff	0x00010000
A2W_PLLB_ANA_SSCS	0x7e1021f0	RW	17	0x0001ffff	0000000000
A2W_PLLA_FRAC	0x7e102200	RW	20	0x000fffff	0000000000
A2W_PLLA_ANA_SSCL	0x7e102210	RW	22	0x003fffff	0000000000
A2W_PLLC_FRAC	0x7e102220	RW	20	0x000fffff	0000000000
A2W_PLLC_ANA_SSCL	0x7e102230	RW	22	0x003fffff	0000000000
A2W_PLLD_FRAC	0x7e102240	RW	20	0x000fffff	0000000000
A2W_PLLD_ANA_SSCL	0x7e102250	RW	22	0x003fffff	0000000000
A2W_PLLH_FRAC	0x7e102260	RW	20	0x000fffff	0000000000
A2W_HDMI_CTL_HFEN	0x7e102280	RW	1	0x00000001	0000000000
A2W_XOSC_CPR	0x7e102290	RW	5	0x00000013	0000000000
A2W_SMPS_A_VOLTS	0x7e1022a0	RW	5	0x0000001f	0000000000
A2W_SMPS_C_CTL	0x7e1022c0	RW	2	0x00000003	0000000000
A2W_SMPS_L_SPA	0x7e1022d0	RW	10	0x000003ff	0000000000
A2W_PLLB_FRAC	0x7e1022e0	RW	20	0x000fffff	0000000000
A2W_PLLB_ANA_SSCL	0x7e1022f0	RW	22	0x003fffff	0000000000
A2W_PLLA_DSI0	0x7e102300	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_KAIP	0x7e102310	RW	11	0x0000077f	0x0000033a
A2W_PLLC_CORE2	0x7e102320	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_KAIP	0x7e102330	RW	11	0x0000077f	0x0000033a
A2W_PLLD_DSI0	0x7e102340	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_KAIP	0x7e102350	RW	11	0x0000077f	0x0000033a
A2W_PLLH_AUX	0x7e102360	RW	10	0x000003ff	0x00000100
A2W_PLLH_ANA_KAIP	0x7e102370	RW	11	0x0000077f	0x0000033a
A2W_XOSC_BIAS	0x7e102390	RW	5	0x0000001f	0x00000018
A2W_SMPS_A_GAIN	0x7e1023a0	RW	3	0x00000007	0000000000
A2W_SMPS_L_SCV	0x7e1023d0	RW	5	0x0000001f	0000000000
A2W_PLLB_ARM	0x7e1023e0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_KAIP	0x7e1023f0	RW	11	0x0000077f	0x0000033a
A2W_PLLA_CORE	0x7e102400	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_STAT	0x7e102410	RW	12	0x00000fff	0000000000
A2W_PLLC_CORE1	0x7e102420	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_STAT	0x7e102430	RW	12	0x00000fff	0000000000
A2W_PLLD_CORE	0x7e102440	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_STAT	0x7e102450	RW	12	0x00000fff	0000000000
A2W_PLLH_RCAL	0x7e102460	RW	10	0x000003ff	0x00000100
A2W_XOSC_PWR	0x7e102490	RW	3	0x00000007	0x00000004
A2W_SMPS_L_SCA	0x7e1024d0	RW	12	0x00000fff	0000000000
A2W_PLLB_SP0	0x7e1024e0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_STAT	0x7e1024f0	RW	12	0x00000fff	0000000000
A2W_PLLA_PER	0x7e102500	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_SCTL	0x7e102510	RW	5	0x0000001f	0000000000
A2W_PLLC_PER	0x7e102520	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_SCTL	0x7e102530	RW	5	0x0000001f	0000000000
A2W_PLLD_PER	0x7e102540	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_SCTL	0x7e102550	RW	5	0x0000001f	0000000000
A2W_PLLH_PIX	0x7e102560	RW	10	0x000003ff	0x00000100
A2W_PLLH_ANA_SCTL	0x7e102570	RW	5	0x0000001f	0000000000
A2W_SMPS_L_SIV	0x7e1025d0	RW	5	0x0000001f	0000000000
A2W_PLLB_SP1	0x7e1025e0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_SCTL	0x7e1025f0	RW	5	0x0000001f	0000000000
A2W_PLLA_CCP2	0x7e102600	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_VCO	0x7e102610	RW	1	0x00000001	0000000000
A2W_PLLC_CORE0	0x7e102620	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_VCO	0x7e102630	RW	1	0x00000001	0000000000
A2W_PLLD_DSI1	0x7e102640	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_VCO	0x7e102650	RW	1	0x00000001	0000000000
A2W_PLLH_ANA_STAT	0x7e102660	RW	21	0x001f1fff	0000000000
A2W_PLLH_ANA_VCO	0x7e102670	RW	1	0x00000001	0000000000
A2W_SMPS_L_SIA	0x7e1026d0	RW	10	0x000003ff	0000000000
A2W_PLLB_SP2	0x7e1026e0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_VCO	0x7e1026f0	RW	1	0x00000001	0000000000
A2W_PLLA_DIG0R	0x7e102800	RW	24	0x00ffffff	0000000000
A2W_PLLA_DIG1R	0x7e102804	RW	24	0x00ffffff	0x00004000
A2W_PLLA_DIG2R	0x7e102808	RW	24	0x00ffffff	0x00100401
A2W_PLLA_DIG3R	0x7e10280c	RW	24	0x00ffffff	0x00000004
A2W_PLLA_ANA0R	0x7e102810	RW	24	0x00ffffff	0000000000
A2W_PLLA_ANA1R	0x7e102814	RW	24	0x00ffffff	0x001d0000
A2W_PLLA_ANA2R	0x7e102818	RW	24	0x00ffffff	0000000000
A2W_PLLA_ANA3R	0x7e10281c	RW	24	0x00ffffff	0x00000180
A2W_PLLC_DIG0R	0x7e102820	RW	24	0x00ffffff	0000000000
A2W_PLLC_DIG1R	0x7e102824	RW	24	0x00ffffff	0x00004000
A2W_PLLC_DIG2R	0x7e102828	RW	24	0x00ffffff	0x00100401
A2W_PLLC_DIG3R	0x7e10282c	RW	24	0x00ffffff	0x00000004
A2W_PLLC_ANA0R	0x7e102830	RW	24	0x00ffffff	0000000000
A2W_PLLC_ANA1R	0x7e102834	RW	24	0x00ffffff	0x001d0000
A2W_PLLC_ANA2R	0x7e102838	RW	24	0x00ffffff	0000000000
A2W_PLLC_ANA3R	0x7e10283c	RW	24	0x00ffffff	0x00000180
A2W_PLLD_DIG0R	0x7e102840	RW	24	0x00ffffff	0000000000
A2W_PLLD_DIG1R	0x7e102844	RW	24	0x00ffffff	0x00004000
A2W_PLLD_DIG2R	0x7e102848	RW	24	0x00ffffff	0x00100401
A2W_PLLD_DIG3R	0x7e10284c	RW	24	0x00ffffff	0x00000004
A2W_PLLD_ANA0R	0x7e102850	RW	24	0x00ffffff	0000000000
A2W_PLLD_ANA1R	0x7e102854	RW	24	0x00ffffff	0x001d0000
A2W_PLLD_ANA2R	0x7e102858	RW	24	0x00ffffff	0000000000
A2W_PLLD_ANA3R	0x7e10285c	RW	24	0x00ffffff	0x00000180
A2W_PLLH_DIG0R	0x7e102860	RW	24	0x00ffffff	0000000000
A2W_PLLH_DIG1R	0x7e102864	RW	24	0x00ffffff	0000000000
A2W_PLLH_DIG2R	0x7e102868	RW	24	0x00ffffff	0x000000aa
A2W_PLLH_DIG3R	0x7e10286c	RW	24	0x00ffffff	0000000000
A2W_PLLH_ANA0R	0x7e102870	RW	24	0x00ffffff	0x00d80000
A2W_PLLH_ANA1R	0x7e102874	RW	24	0x00ffffff	0x00000014
A2W_PLLH_ANA2R	0x7e102878	RW	24	0x00ffffff	0000000000
A2W_PLLH_ANA3R	0x7e10287c	RW	24	0x00ffffff	0000000000
A2W_HDMI_CTL0R	0x7e102880	RW	24	0x00ffffff	0x00470238
A2W_HDMI_CTL1R	0x7e102884	RW	24	0x00ffffff	0x00011c00
A2W_HDMI_CTL2R	0x7e102888	RW	24	0x00ffffff	0x0018048e
A2W_HDMI_CTL3R	0x7e10288c	RW	24	0x00ffffff	0x00000040
A2W_XOSC0R	0x7e102890	RW	24	0x00ffffff	0x00820080
A2W_XOSC1R	0x7e102894	RW	24	0x00ffffff	0x00000006
A2W_SMPS_CTLA0R	0x7e1028a0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLA1R	0x7e1028a4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLA2R	0x7e1028a8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB0R	0x7e1028b0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB1R	0x7e1028b4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLB2R	0x7e1028b8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC0R	0x7e1028c0	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC1R	0x7e1028c4	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC2R	0x7e1028c8	RW	24	0x00ffffff	0000000000
A2W_SMPS_CTLC3R	0x7e1028cc	RW	24	0x00ffffff	0000000000
A2W_SMPS_LDO0R	0x7e1028d0	RW	24	0x00ffffff	0000000000
A2W_SMPS_LDO1R	0x7e1028d4	RW	24	0x00ffffff	0000000000
A2W_PLLB_DIG0R	0x7e1028e0	RW	24	0x00ffffff	0000000000
A2W_PLLB_DIG1R	0x7e1028e4	RW	24	0x00ffffff	0x00004000
A2W_PLLB_DIG2R	0x7e1028e8	RW	24	0x00ffffff	0x00100401
A2W_PLLB_DIG3R	0x7e1028ec	RW	24	0x00ffffff	0x00000004
A2W_PLLB_ANA0R	0x7e1028f0	RW	24	0x00ffffff	0000000000
A2W_PLLB_ANA1R	0x7e1028f4	RW	24	0x00ffffff	0x001d0000
A2W_PLLB_ANA2R	0x7e1028f8	RW	24	0x00ffffff	0000000000
A2W_PLLB_ANA3R	0x7e1028fc	RW	24	0x00ffffff	0x00000180
A2W_PLLA_CTRLR	0x7e102900	RW	18	0x000373ff	0x00010000
A2W_PLLA_ANA_SSCSR	0x7e102910	RW	17	0x0001ffff	0000000000
A2W_PLLC_CTRLR	0x7e102920	RW	18	0x000373ff	0x00010000
A2W_PLLC_ANA_SSCSR	0x7e102930	RW	17	0x0001ffff	0000000000
A2W_PLLD_CTRLR	0x7e102940	RW	18	0x000373ff	0x00010000
A2W_PLLD_ANA_SSCSR	0x7e102950	RW	17	0x0001ffff	0000000000
A2W_PLLH_CTRLR	0x7e102960	RW	18	0x000370ff	0x00010000
A2W_HDMI_CTL_RCALR	0x7e102980	RW	17	0x00011f33	0x00010000
A2W_XOSC_CTRLR	0x7e102990	RW	8	0x000000ff	0000000000
A2W_SMPS_A_MODER	0x7e1029a0	RW	1	0x00000001	0000000000
A2W_SMPS_B_STATR	0x7e1029b0	RW	13	0x0000111f	0000000000
A2W_SMPS_C_CLKR	0x7e1029c0	RW	4	0x0000000f	0000000000
A2W_SMPS_L_SPVR	0x7e1029d0	RW	5	0x0000001f	0000000000
A2W_PLLB_CTRLR	0x7e1029e0	RW	18	0x000373ff	0x00010000
A2W_PLLB_ANA_SSCSR	0x7e1029f0	RW	17	0x0001ffff	0000000000
A2W_PLLA_FRACR	0x7e102a00	RW	20	0x000fffff	0000000000
A2W_PLLA_ANA_SSCLR	0x7e102a10	RW	17	0x0001ffff	0000000000
A2W_PLLC_FRACR	0x7e102a20	RW	20	0x000fffff	0000000000
A2W_PLLC_ANA_SSCLR	0x7e102a30	RW	17	0x0001ffff	0000000000
A2W_PLLD_FRACR	0x7e102a40	RW	20	0x000fffff	0000000000
A2W_PLLD_ANA_SSCLR	0x7e102a50	RW	17	0x0001ffff	0000000000
A2W_PLLH_FRACR	0x7e102a60	RW	20	0x000fffff	0000000000
A2W_HDMI_CTL_HFENR	0x7e102a80	RW	1	0x00000001	0000000000
A2W_XOSC_CPRR	0x7e102a90	RW	5	0x00000013	0000000000
A2W_SMPS_A_VOLTSR	0x7e102aa0	RW	5	0x0000001f	0000000000
A2W_SMPS_C_CTLR	0x7e102ac0	RW	2	0x00000003	0000000000
A2W_SMPS_L_SPAR	0x7e102ad0	RW	10	0x000003ff	0000000000
A2W_PLLB_FRACR	0x7e102ae0	RW	20	0x000fffff	0000000000
A2W_PLLB_ANA_SSCLR	0x7e102af0	RW	17	0x0001ffff	0000000000
A2W_PLLA_DSI0R	0x7e102b00	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_KAIPR	0x7e102b10	RW	11	0x0000077f	0x0000033a
A2W_PLLC_CORE2R	0x7e102b20	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_KAIPR	0x7e102b30	RW	11	0x0000077f	0x0000033a
A2W_PLLD_DSI0R	0x7e102b40	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_KAIPR	0x7e102b50	RW	11	0x0000077f	0x0000033a
A2W_PLLH_AUXR	0x7e102b60	RW	10	0x000003ff	0x00000100
A2W_PLLH_ANA_KAIPR	0x7e102b70	RW	11	0x0000077f	0x0000033a
A2W_XOSC_BIASR	0x7e102b90	RW	5	0x0000001f	0x00000018
A2W_SMPS_A_GAINR	0x7e102ba0	RW	3	0x00000007	0000000000
A2W_SMPS_L_SCVR	0x7e102bd0	RW	5	0x0000001f	0000000000
A2W_PLLB_ARMR	0x7e102be0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_KAIPR	0x7e102bf0	RW	11	0x0000077f	0x0000033a
A2W_PLLA_CORER	0x7e102c00	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_STATR	0x7e102c10	RW	12	0x00000fff	0000000000
A2W_PLLC_CORE1R	0x7e102c20	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_STATR	0x7e102c30	RW	12	0x00000fff	0000000000
A2W_PLLD_CORER	0x7e102c40	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_STATR	0x7e102c50	RW	12	0x00000fff	0000000000
A2W_PLLH_RCALR	0x7e102c60	RW	10	0x000003ff	0x00000100
A2W_XOSC_PWRR	0x7e102c90	RW	3	0x00000007	0x00000004
A2W_SMPS_L_SCAR	0x7e102cd0	RW	12	0x00000fff	0000000000
A2W_PLLB_SP0R	0x7e102ce0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_STATR	0x7e102cf0	RW	12	0x00000fff	0000000000
A2W_PLLA_PERR	0x7e102d00	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_SCTLR	0x7e102d10	RW	5	0x0000001f	0000000000
A2W_PLLC_PERR	0x7e102d20	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_SCTLR	0x7e102d30	RW	5	0x0000001f	0000000000
A2W_PLLD_PERR	0x7e102d40	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_SCTLR	0x7e102d50	RW	5	0x0000001f	0000000000
A2W_PLLH_PIXR	0x7e102d60	RW	10	0x000003ff	0x00000100
A2W_PLLH_ANA_SCTLR	0x7e102d70	RW	5	0x0000001f	0000000000
A2W_SMPS_L_SIVR	0x7e102dd0	RW	5	0x0000001f	0000000000
A2W_PLLB_SP1R	0x7e102de0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_SCTLR	0x7e102df0	RW	5	0x0000001f	0000000000
A2W_PLLA_CCP2R	0x7e102e00	RW	10	0x000003ff	0x00000100
A2W_PLLA_ANA_VCOR	0x7e102e10	RW	1	0x00000001	0000000000
A2W_PLLC_CORE0R	0x7e102e20	RW	10	0x000003ff	0x00000100
A2W_PLLC_ANA_VCOR	0x7e102e30	RW	1	0x00000001	0000000000
A2W_PLLD_DSI1R	0x7e102e40	RW	10	0x000003ff	0x00000100
A2W_PLLD_ANA_VCOR	0x7e102e50	RW	1	0x00000001	0000000000
A2W_PLLH_ANA_STATR	0x7e102e60	RW	21	0x001f1fff	0000000000
A2W_PLLH_ANA_VCOR	0x7e102e70	RW	1	0x00000001	0000000000
A2W_SMPS_L_SIAR	0x7e102ed0	RW	10	0x000003ff	0000000000
A2W_PLLB_SP2R	0x7e102ee0	RW	10	0x000003ff	0x00000100
A2W_PLLB_ANA_VCOR	0x7e102ef0	RW	1	0x00000001	0000000000
A2W_PLLA_MULTI	0x7e102f00	RW	0	0000000000	0000000000
A2W_PLLA_ANA_MULTI	0x7e102f10	RW	0	0000000000	0000000000
A2W_PLLC_MULTI	0x7e102f20	RW	0	0000000000	0000000000
A2W_PLLC_ANA_MULTI	0x7e102f30	RW	0	0000000000	0000000000
A2W_PLLD_MULTI	0x7e102f40	RW	0	0000000000	0000000000
A2W_PLLD_ANA_MULTI	0x7e102f50	RW	0	0000000000	0000000000
A2W_PLLH_MULTI	0x7e102f60	RW	0	0000000000	0000000000
A2W_PLLH_ANA_MULTI	0x7e102f70	RW	0	0000000000	0000000000
A2W_HDMI_CTL_MULTI	0x7e102f80	RW	0	0000000000	0000000000
A2W_XOSC_MULTI	0x7e102f90	RW	0	0000000000	0000000000
A2W_SMPS_A_MULTI	0x7e102fa0	RW	0	0000000000	0000000000
A2W_SMPS_B_MULTI	0x7e102fb0	RW	0	0000000000	0000000000
A2W_SMPS_C_MULTI	0x7e102fc0	RW	0	0000000000	0000000000
A2W_SMPS_L_MULTI	0x7e102fd0	RW	0	0000000000	0000000000
A2W_PLLB_MULTI	0x7e102fe0	RW	0	0000000000	0000000000
A2W_PLLB_ANA_MULTI	0x7e102ff0	RW	0	0000000000	0000000000

Register:A2W_PLLA_CTRL (0x7e102100)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_CTRL_NDIV	0	9	0x000003ff	0xfffffc00	0x0
missing definiton	10	11	NA	NA	NA
A2W_PLLA_CTRL_PDIV	12	14	0x00007000	0xffff8fff	0x0
missing definiton	15	15	NA	NA	NA
A2W_PLLA_CTRL_PWRDN	16	16	0x00010000	0xfffeffff	0x1
A2W_PLLA_CTRL_PRSTN	17	17	0x00020000	0xfffdffff	0x0

Register:A2W_PLLA_ANA_SSCS (0x7e102110)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_SSCS_STEP	0	15	0x0000ffff	0xffff0000	0x0
A2W_PLLA_ANA_SSCS_MODE	16	16	0x00010000	0xfffeffff	0x0

Register:A2W_PLLC_CTRL (0x7e102120)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_CTRL_NDIV	0	9	0x000003ff	0xfffffc00	0x0
missing definiton	10	11	NA	NA	NA
A2W_PLLC_CTRL_PDIV	12	14	0x00007000	0xffff8fff	0x0
missing definiton	15	15	NA	NA	NA
A2W_PLLC_CTRL_PWRDN	16	16	0x00010000	0xfffeffff	0x1
A2W_PLLC_CTRL_PRSTN	17	17	0x00020000	0xfffdffff	0x0

Register:A2W_PLLC_ANA_SSCS (0x7e102130)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_ANA_SSCS_STEP	0	15	0x0000ffff	0xffff0000	0x0
A2W_PLLC_ANA_SSCS_MODE	16	16	0x00010000	0xfffeffff	0x0

Register:A2W_PLLD_CTRL (0x7e102140)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_CTRL_NDIV	0	9	0x000003ff	0xfffffc00	0x0
missing definiton	10	11	NA	NA	NA
A2W_PLLD_CTRL_PDIV	12	14	0x00007000	0xffff8fff	0x0
missing definiton	15	15	NA	NA	NA
A2W_PLLD_CTRL_PWRDN	16	16	0x00010000	0xfffeffff	0x1
A2W_PLLD_CTRL_PRSTN	17	17	0x00020000	0xfffdffff	0x0

Register:A2W_PLLD_ANA_SSCS (0x7e102150)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_ANA_SSCS_STEP	0	15	0x0000ffff	0xffff0000	0x0
A2W_PLLD_ANA_SSCS_MODE	16	16	0x00010000	0xfffeffff	0x0

Register:A2W_PLLH_CTRL (0x7e102160)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_CTRL_NDIV	0	7	0x000000ff	0xffffff00	0x0
missing definiton	8	11	NA	NA	NA
A2W_PLLH_CTRL_PDIV	12	14	0x00007000	0xffff8fff	0x0
missing definiton	15	15	NA	NA	NA
A2W_PLLH_CTRL_PWRDN	16	16	0x00010000	0xfffeffff	0x1
A2W_PLLH_CTRL_PRSTN	17	17	0x00020000	0xfffdffff	0x0

Register:A2W_HDMI_CTL_RCAL (0x7e102180)

field_name	start_bit	end_bit	set	clear	reset
A2W_HDMI_CTL_RCAL_SELAVG	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	3	NA	NA	NA
A2W_HDMI_CTL_RCAL_SELDIV	4	5	0x00000030	0xffffffcf	0x0
missing definiton	6	7	NA	NA	NA
A2W_HDMI_CTL_RCAL_MANR	8	11	0x00000f00	0xfffff0ff	0x0
A2W_HDMI_CTL_RCAL_MANREN	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
A2W_HDMI_CTL_RCAL_RSTB	16	16	0x00010000	0xfffeffff	0x1

Register:A2W_XOSC_CTRL (0x7e102190)

field_name	start_bit	end_bit	set	clear	reset
A2W_XOSC_CTRL_PLLCEN	0	0	0x00000001	0xfffffffe	0x0
A2W_XOSC_CTRL_HDMIEN	1	1	0x00000002	0xfffffffd	0x0
A2W_XOSC_CTRL_USBEN	2	2	0x00000004	0xfffffffb	0x0
A2W_XOSC_CTRL_SMPSEN	3	3	0x00000008	0xfffffff7	0x0
A2W_XOSC_CTRL_DDREN	4	4	0x00000010	0xffffffef	0x0
A2W_XOSC_CTRL_PLLDEN	5	5	0x00000020	0xffffffdf	0x0
A2W_XOSC_CTRL_PLLAEN	6	6	0x00000040	0xffffffbf	0x0
A2W_XOSC_CTRL_PLLBEN	7	7	0x00000080	0xffffff7f	0x0
missing definiton	8	11	NA	NA	NA
A2W_XOSC_CTRL_PLLCOK	12	12	0x00001000	0xffffefff	0x0
A2W_XOSC_CTRL_HDMIOK	13	13	0x00002000	0xffffdfff	0x0
A2W_XOSC_CTRL_USBOK	14	14	0x00004000	0xffffbfff	0x0
A2W_XOSC_CTRL_SMPSOK	15	15	0x00008000	0xffff7fff	0x0
A2W_XOSC_CTRL_DDROK	16	16	0x00010000	0xfffeffff	0x0
A2W_XOSC_CTRL_PLLDOK	17	17	0x00020000	0xfffdffff	0x0
A2W_XOSC_CTRL_PLLAOK	18	18	0x00040000	0xfffbffff	0x0
A2W_XOSC_CTRL_PLLBOK	19	19	0x00080000	0xfff7ffff	0x0

Register:A2W_SMPS_A_MODE (0x7e1021a0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_A_MODE_BSTPWMB	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_SMPS_B_STAT (0x7e1021b0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_B_STAT_VOLTS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
A2W_SMPS_B_STAT_BSTPWMB	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
A2W_SMPS_B_STAT_POK	12	12	0x00001000	0xffffefff	0x0

Register:A2W_SMPS_C_CLK (0x7e1021c0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_C_CLK_OSCDIV	0	1	0x00000003	0xfffffffc	0x0
A2W_SMPS_C_CLK_USEOSC	2	2	0x00000004	0xfffffffb	0x0
A2W_SMPS_C_CLK_TDEN	3	3	0x00000008	0xfffffff7	0x0

Register:A2W_SMPS_L_SPV (0x7e1021d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SPV_VOLTS	0	4	0x0000001f	0xffffffe0	0x0

Register:A2W_PLLB_CTRL (0x7e1021e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_CTRL_NDIV	0	9	0x000003ff	0xfffffc00	0x0
missing definiton	10	11	NA	NA	NA
A2W_PLLB_CTRL_PDIV	12	14	0x00007000	0xffff8fff	0x0
missing definiton	15	15	NA	NA	NA
A2W_PLLB_CTRL_PWRDN	16	16	0x00010000	0xfffeffff	0x1
A2W_PLLB_CTRL_PRSTN	17	17	0x00020000	0xfffdffff	0x0

Register:A2W_PLLB_ANA_SSCS (0x7e1021f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_SSCS_STEP	0	15	0x0000ffff	0xffff0000	0x0
A2W_PLLB_ANA_SSCS_MODE	16	16	0x00010000	0xfffeffff	0x0

Register:A2W_PLLA_FRAC (0x7e102200)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_FRAC_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:A2W_PLLA_ANA_SSCL (0x7e102210)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_SSCL_LIMIT	0	21	0x003fffff	0xffc00000	0x0

Register:A2W_PLLC_FRAC (0x7e102220)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_FRAC_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:A2W_PLLD_FRAC (0x7e102240)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_FRAC_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:A2W_PLLH_FRAC (0x7e102260)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_FRAC_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:A2W_HDMI_CTL_HFEN (0x7e102280)

field_name	start_bit	end_bit	set	clear	reset
A2W_HDMI_CTL_HFEN_HFEN	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_XOSC_CPR (0x7e102290)

field_name	start_bit	end_bit	set	clear	reset
A2W_XOSC_CPR_DIV	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	3	NA	NA	NA
A2W_XOSC_CPR_CPR1	4	4	0x00000010	0xffffffef	0x0

Register:A2W_SMPS_A_VOLTS (0x7e1022a0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_A_VOLTS_VOLTS	0	4	0x0000001f	0xffffffe0	0x0

Register:A2W_SMPS_C_CTL (0x7e1022c0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_C_CTL_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
A2W_SMPS_C_CTL_UPEN	1	1	0x00000002	0xfffffffd	0x0

Register:A2W_SMPS_L_SPA (0x7e1022d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SPA_ANA	0	9	0x000003ff	0xfffffc00	0x0

Register:A2W_PLLB_FRAC (0x7e1022e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_FRAC_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:A2W_PLLB_ANA_SSCL (0x7e1022f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_SSCL_LIMIT	0	21	0x003fffff	0xffc00000	0x0

Register:A2W_PLLA_DSI0 (0x7e102300)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_DSI0_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLA_DSI0_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLA_DSI0_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLA_ANA_KAIP (0x7e102310)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_KAIP_KP	0	3	0x0000000f	0xfffffff0	0xa
A2W_PLLA_ANA_KAIP_KI	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
A2W_PLLA_ANA_KAIP_KA	8	10	0x00000700	0xfffff8ff	0x3

Register:A2W_PLLC_CORE2 (0x7e102320)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_CORE2_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLC_CORE2_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLC_CORE2_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLC_ANA_KAIP (0x7e102330)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_ANA_KAIP_KP	0	3	0x0000000f	0xfffffff0	0xa
A2W_PLLC_ANA_KAIP_KI	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
A2W_PLLC_ANA_KAIP_KA	8	10	0x00000700	0xfffff8ff	0x3

Register:A2W_PLLD_DSI0 (0x7e102340)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_DSI0_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLD_DSI0_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLD_DSI0_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLD_ANA_KAIP (0x7e102350)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_ANA_KAIP_KP	0	3	0x0000000f	0xfffffff0	0xa
A2W_PLLD_ANA_KAIP_KI	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
A2W_PLLD_ANA_KAIP_KA	8	10	0x00000700	0xfffff8ff	0x3

Register:A2W_PLLH_AUX (0x7e102360)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_AUX_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLH_AUX_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLH_AUX_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLH_ANA_KAIP (0x7e102370)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_ANA_KAIP_KP	0	3	0x0000000f	0xfffffff0	0xa
A2W_PLLH_ANA_KAIP_KI	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
A2W_PLLH_ANA_KAIP_KA	8	10	0x00000700	0xfffff8ff	0x3

Register:A2W_XOSC_BIAS (0x7e102390)

field_name	start_bit	end_bit	set	clear	reset
A2W_XOSC_BIAS_BIAS	0	3	0x0000000f	0xfffffff0	0x8
A2W_XOSC_BIAS_HIGHP	4	4	0x00000010	0xffffffef	0x1

Register:A2W_SMPS_A_GAIN (0x7e1023a0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_A_GAIN_DIGGAIN	0	2	0x00000007	0xfffffff8	0x0

Register:A2W_SMPS_L_SCV (0x7e1023d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SCV_VOLTS	0	4	0x0000001f	0xffffffe0	0x0

Register:A2W_PLLB_ARM (0x7e1023e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ARM_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLB_ARM_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLB_ARM_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLB_ANA_KAIP (0x7e1023f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_KAIP_KP	0	3	0x0000000f	0xfffffff0	0xa
A2W_PLLB_ANA_KAIP_KI	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
A2W_PLLB_ANA_KAIP_KA	8	10	0x00000700	0xfffff8ff	0x3

Register:A2W_PLLA_CORE (0x7e102400)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_CORE_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLA_CORE_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLA_CORE_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLA_ANA_STAT (0x7e102410)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_STAT_DATA	0	11	0x00000fff	0xfffff000	0x0

Register:A2W_PLLC_CORE1 (0x7e102420)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_CORE1_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLC_CORE1_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLC_CORE1_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLC_ANA_STAT (0x7e102430)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_ANA_STAT_DATA	0	11	0x00000fff	0xfffff000	0x0

Register:A2W_PLLD_CORE (0x7e102440)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_CORE_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLD_CORE_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLD_CORE_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLD_ANA_STAT (0x7e102450)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_ANA_STAT_DATA	0	11	0x00000fff	0xfffff000	0x0

Register:A2W_PLLH_RCAL (0x7e102460)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_RCAL_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLH_RCAL_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLH_RCAL_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_XOSC_PWR (0x7e102490)

field_name	start_bit	end_bit	set	clear	reset
A2W_XOSC_PWR_BYPASS	0	0	0x00000001	0xfffffffe	0x0
A2W_XOSC_PWR_PWRDN	1	1	0x00000002	0xfffffffd	0x0
A2W_XOSC_PWR_RSTB	2	2	0x00000004	0xfffffffb	0x1

Register:A2W_SMPS_L_SCA (0x7e1024d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SCA_ANA	0	11	0x00000fff	0xfffff000	0x0

Register:A2W_PLLB_SP0 (0x7e1024e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_SP0_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLB_SP0_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLB_SP0_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLB_ANA_STAT (0x7e1024f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_STAT_DATA	0	11	0x00000fff	0xfffff000	0x0

Register:A2W_PLLA_PER (0x7e102500)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_PER_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLA_PER_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLA_PER_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLA_ANA_SCTL (0x7e102510)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_SCTL_SEL	0	2	0x00000007	0xfffffff8	0x0
A2W_PLLA_ANA_SCTL_UPDATE	3	3	0x00000008	0xfffffff7	0x0
A2W_PLLA_ANA_SCTL_RESET	4	4	0x00000010	0xffffffef	0x0

Register:A2W_PLLC_PER (0x7e102520)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_PER_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLC_PER_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLC_PER_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLC_ANA_SCTL (0x7e102530)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_ANA_SCTL_SEL	0	2	0x00000007	0xfffffff8	0x0
A2W_PLLC_ANA_SCTL_UPDATE	3	3	0x00000008	0xfffffff7	0x0
A2W_PLLC_ANA_SCTL_RESET	4	4	0x00000010	0xffffffef	0x0

Register:A2W_PLLD_PER (0x7e102540)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_PER_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLD_PER_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLD_PER_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLD_ANA_SCTL (0x7e102550)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_ANA_SCTL_SEL	0	2	0x00000007	0xfffffff8	0x0
A2W_PLLD_ANA_SCTL_UPDATE	3	3	0x00000008	0xfffffff7	0x0
A2W_PLLD_ANA_SCTL_RESET	4	4	0x00000010	0xffffffef	0x0

Register:A2W_PLLH_PIX (0x7e102560)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_PIX_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLH_PIX_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLH_PIX_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLH_ANA_SCTL (0x7e102570)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_ANA_SCTL_SEL	0	2	0x00000007	0xfffffff8	0x0
A2W_PLLH_ANA_SCTL_UPDATE	3	3	0x00000008	0xfffffff7	0x0
A2W_PLLH_ANA_SCTL_RESET	4	4	0x00000010	0xffffffef	0x0

Register:A2W_SMPS_L_SIV (0x7e1025d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SIV_VOLTS	0	4	0x0000001f	0xffffffe0	0x0

Register:A2W_PLLB_SP1 (0x7e1025e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_SP1_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLB_SP1_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLB_SP1_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLB_ANA_SCTL (0x7e1025f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_SCTL_SEL	0	2	0x00000007	0xfffffff8	0x0
A2W_PLLB_ANA_SCTL_UPDATE	3	3	0x00000008	0xfffffff7	0x0
A2W_PLLB_ANA_SCTL_RESET	4	4	0x00000010	0xffffffef	0x0

Register:A2W_PLLA_CCP2 (0x7e102600)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_CCP2_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLA_CCP2_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLA_CCP2_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLA_ANA_VCO (0x7e102610)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLA_ANA_VCO_RANGE	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_PLLC_CORE0 (0x7e102620)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_CORE0_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLC_CORE0_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLC_CORE0_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLC_ANA_VCO (0x7e102630)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLC_ANA_VCO_RANGE	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_PLLD_DSI1 (0x7e102640)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_DSI1_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLD_DSI1_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLD_DSI1_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLD_ANA_VCO (0x7e102650)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLD_ANA_VCO_RANGE	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_PLLH_ANA_STAT (0x7e102660)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_ANA_STAT_DATA	0	11	0x00000fff	0xfffff000	0x0
A2W_PLLH_ANA_STAT_RCALDONE	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
A2W_PLLH_ANA_STAT_RCALCODE	16	19	0x000f0000	0xfff0ffff	0x0
A2W_PLLH_ANA_STAT_CNTLENB	20	20	0x00100000	0xffefffff	0x0

Register:A2W_PLLH_ANA_VCO (0x7e102670)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLH_ANA_VCO_RANGE	0	0	0x00000001	0xfffffffe	0x0

Register:A2W_SMPS_L_SIA (0x7e1026d0)

field_name	start_bit	end_bit	set	clear	reset
A2W_SMPS_L_SIA_ANA	0	9	0x000003ff	0xfffffc00	0x0

Register:A2W_PLLB_SP2 (0x7e1026e0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_SP2_DIV	0	7	0x000000ff	0xffffff00	0x0
A2W_PLLB_SP2_CHENB	8	8	0x00000100	0xfffffeff	0x1
A2W_PLLB_SP2_BYPEN	9	9	0x00000200	0xfffffdff	0x0

Register:A2W_PLLB_ANA_VCO (0x7e1026f0)

field_name	start_bit	end_bit	set	clear	reset
A2W_PLLB_ANA_VCO_RANGE	0	0	0x00000001	0xfffffffe	0x0

APERF0

Info

base	0x7e009800
id	0x41584950

Registers

register name	address	type	width	mask
APERF0_GEN_CTRL	0x7e009800	RW	2	0x00000003
APERF0_BW0_CTRL	0x7e009840	RW	32	0xf0001f1f
APERF0_BW0_ATRANS	0x7e009844	RO	32	0xffffffff
APERF0_BW0_ATWAIT	0x7e009848	RO	32	0xffffffff
APERF0_BW0_AMAX	0x7e00984c	RO	24	0x00ffffff
APERF0_BW0_WTRANS	0x7e009850	RO	32	0xffffffff
APERF0_BW0_WTWAIT	0x7e009854	RO	32	0xffffffff
APERF0_BW0_WMAX	0x7e009858	RO	24	0x00ffffff
APERF0_BW0_RTRANS	0x7e00985c	RO	32	0xffffffff
APERF0_BW0_RTWAIT	0x7e009860	RO	32	0xffffffff
APERF0_BW0_RMAX	0x7e009864	RO	24	0x00ffffff
APERF0_BW1_RPEND	0x7e009868	RO	8	0x000000ff
APERF0_BW2_RPEND	0x7e009868	RO	8	0x000000ff
APERF0_BW0_RPEND	0x7e009868	RO	8	0x000000ff
APERF0_BW1_CTRL	0x7e009880	RW	32	0xf0001f1f
APERF0_BW1_ATRANS	0x7e009884	RO	32	0xffffffff
APERF0_BW1_ATWAIT	0x7e009888	RO	32	0xffffffff
APERF0_BW1_AMAX	0x7e00988c	RO	24	0x00ffffff
APERF0_BW1_WTRANS	0x7e009890	RO	32	0xffffffff
APERF0_BW1_WTWAIT	0x7e009894	RO	32	0xffffffff
APERF0_BW1_WMAX	0x7e009898	RO	16	0x0000ffff
APERF0_BW1_RTRANS	0x7e00989c	RO	32	0xffffffff
APERF0_BW1_RTWAIT	0x7e0098a0	RO	32	0xffffffff
APERF0_BW1_RMAX	0x7e0098a4	RO	24	0x00ffffff
APERF0_BW2_CTRL	0x7e0098c0	RW	32	0xf0001f1f
APERF0_BW2_ATRANS	0x7e0098c4	RO	32	0xffffffff
APERF0_BW2_ATWAIT	0x7e0098c8	RO	32	0xffffffff
APERF0_BW2_AMAX	0x7e0098cc	RO	24	0x00ffffff
APERF0_BW2_WTRANS	0x7e0098d0	RO	32	0xffffffff
APERF0_BW2_WTWAIT	0x7e0098d4	RO	32	0xffffffff
APERF0_BW2_WMAX	0x7e0098d8	RO	28	0x0ff0ffff
APERF0_BW2_RTRANS	0x7e0098dc	RO	32	0xffffffff
APERF0_BW2_RTWAIT	0x7e0098e0	RO	32	0xffffffff
APERF0_BW2_RMAX	0x7e0098e4	RO	24	0x00ffffff

Register:APERF0_GEN_CTRL (0x7e009800)

field_name	start_bit	end_bit	set	clear	reset
APERF0_GEN_CTRL_ENABLE	0	0	0x00000001	0xfffffffe	0x0
APERF0_GEN_CTRL_RESET	1	1	0x00000002	0xfffffffd	0x0

Register:APERF0_BW0_CTRL (0x7e009840)

field_name	start_bit	end_bit	set	clear	reset
APERF0_BW0_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF0_BW0_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF0_BW0_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF0_BW0_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF0_BW0_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF0_BW0_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:APERF0_BW1_CTRL (0x7e009880)

field_name	start_bit	end_bit	set	clear	reset
APERF0_BW1_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF0_BW1_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF0_BW1_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF0_BW1_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF0_BW1_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF0_BW1_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:APERF0_BW2_CTRL (0x7e0098c0)

field_name	start_bit	end_bit	set	clear	reset
APERF0_BW2_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF0_BW2_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF0_BW2_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF0_BW2_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF0_BW2_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF0_BW2_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

APERF1

Info

base	0x7ee08000
id	0x41584950

Registers

register name	address	type	width	mask
APERF1_GEN_CTRL	0x7ee08000	RW	2	0x00000003
APERF1_BW0_CTRL	0x7ee08040	RW	32	0xf0001f1f
APERF1_BW0_ATRANS	0x7ee08044	RO	32	0xffffffff
APERF1_BW0_ATWAIT	0x7ee08048	RO	32	0xffffffff
APERF1_BW0_AMAX	0x7ee0804c	RO	24	0x00ffffff
APERF1_BW0_WTRANS	0x7ee08050	RO	32	0xffffffff
APERF1_BW0_WTWAIT	0x7ee08054	RO	32	0xffffffff
APERF1_BW0_WMAX	0x7ee08058	RO	24	0x00ffffff
APERF1_BW0_RTRANS	0x7ee0805c	RO	32	0xffffffff
APERF1_BW0_RTWAIT	0x7ee08060	RO	32	0xffffffff
APERF1_BW0_RMAX	0x7ee08064	RO	24	0x00ffffff
APERF1_BW0_RPEND	0x7ee08068	RO	8	0x000000ff
APERF1_BW1_RPEND	0x7ee08068	RO	8	0x000000ff
APERF1_BW2_RPEND	0x7ee08068	RO	8	0x000000ff
APERF1_BW1_CTRL	0x7ee08080	RW	32	0xf0001f1f
APERF1_BW1_ATRANS	0x7ee08084	RO	32	0xffffffff
APERF1_BW1_ATWAIT	0x7ee08088	RO	32	0xffffffff
APERF1_BW1_AMAX	0x7ee0808c	RO	24	0x00ffffff
APERF1_BW1_WTRANS	0x7ee08090	RO	32	0xffffffff
APERF1_BW1_WTWAIT	0x7ee08094	RO	32	0xffffffff
APERF1_BW1_WMAX	0x7ee08098	RO	16	0x0000ffff
APERF1_BW1_RTRANS	0x7ee0809c	RO	32	0xffffffff
APERF1_BW1_RTWAIT	0x7ee080a0	RO	32	0xffffffff
APERF1_BW1_RMAX	0x7ee080a4	RO	24	0x00ffffff
APERF1_BW2_CTRL	0x7ee080c0	RW	32	0xf0001f1f
APERF1_BW2_ATRANS	0x7ee080c4	RO	32	0xffffffff
APERF1_BW2_ATWAIT	0x7ee080c8	RO	32	0xffffffff
APERF1_BW2_AMAX	0x7ee080cc	RO	24	0x00ffffff
APERF1_BW2_WTRANS	0x7ee080d0	RO	32	0xffffffff
APERF1_BW2_WTWAIT	0x7ee080d4	RO	32	0xffffffff
APERF1_BW2_WMAX	0x7ee080d8	RO	28	0x0ff0ffff
APERF1_BW2_RTRANS	0x7ee080dc	RO	32	0xffffffff
APERF1_BW2_RTWAIT	0x7ee080e0	RO	32	0xffffffff
APERF1_BW2_RMAX	0x7ee080e4	RO	24	0x00ffffff

Register:APERF1_GEN_CTRL (0x7ee08000)

field_name	start_bit	end_bit	set	clear	reset
APERF1_GEN_CTRL_ENABLE	0	0	0x00000001	0xfffffffe	0x0
APERF1_GEN_CTRL_RESET	1	1	0x00000002	0xfffffffd	0x0

Register:APERF1_BW0_CTRL (0x7ee08040)

field_name	start_bit	end_bit	set	clear	reset
APERF1_BW0_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF1_BW0_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF1_BW0_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF1_BW0_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF1_BW0_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF1_BW0_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:APERF1_BW1_CTRL (0x7ee08080)

field_name	start_bit	end_bit	set	clear	reset
APERF1_BW1_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF1_BW1_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF1_BW1_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF1_BW1_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF1_BW1_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF1_BW1_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:APERF1_BW2_CTRL (0x7ee080c0)

field_name	start_bit	end_bit	set	clear	reset
APERF1_BW2_CTRL_BUS	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	7	NA	NA	NA
APERF1_BW2_CTRL_ID	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	27	NA	NA	NA
APERF1_BW2_CTRL_LATHALT	28	28	0x10000000	0xefffffff	0x0
APERF1_BW2_CTRL_ID_EN	29	29	0x20000000	0xdfffffff	0x0
APERF1_BW2_CTRL_EN	30	30	0x40000000	0xbfffffff	0x0
APERF1_BW2_CTRL_RESET	31	31	0x80000000	0x7fffffff	0x0

APHY_CSR

Info

description	SDRAM Adress (pin) control
base	0x7ee06000

Registers

register name	address	type
APHY_CSR_ADDR_REV_ID	0x7ee06000	RW
APHY_CSR_GLBL_ADDR_DLL_RESET	0x7ee06004	RW
APHY_CSR_GLBL_ADDR_DLL_RECAL	0x7ee06008	RW
APHY_CSR_GLBL_ADDR_DLL_CNTRL	0x7ee0600c	RW
APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL	0x7ee06010	RW
APHY_CSR_ADDR_MASTER_DLL_OUTPUT	0x7ee06014	RW
APHY_CSR_ADDR_SLAVE_DLL_OFFSET	0x7ee06018	RW
APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN	0x7ee0601c	RW
APHY_CSR_GLBL_ADR_DLL_LOCK_STAT	0x7ee06020	RW
APHY_CSR_DDR_PLL_GLOBAL_RESET	0x7ee06024	RW
APHY_CSR_DDR_PLL_POST_DIV_RESET	0x7ee06028	RW
APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0	0x7ee0602c	RW
APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1	0x7ee06030	RW
APHY_CSR_DDR_PLL_MDIV_VALUE	0x7ee06034	RW
APHY_CSR_DDR_PLL_CONFIG_CNTRL	0x7ee06038	RW
APHY_CSR_DDR_PLL_MISC_CNTRL	0x7ee0603c	RW
APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0	0x7ee06040	RW
APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1	0x7ee06044	RW
APHY_CSR_DDR_PLL_LOCK_STATUS	0x7ee06048	RW
APHY_CSR_DDR_PLL_HOLD_CH	0x7ee0604c	RW
APHY_CSR_DDR_PLL_ENABLE_CH	0x7ee06050	RW
APHY_CSR_DDR_PLL_BYPASS	0x7ee06054	RW
APHY_CSR_DDR_PLL_PWRDWN	0x7ee06058	RW
APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL	0x7ee0605c	RW
APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL	0x7ee06060	RW
APHY_CSR_DDR_PLL_DESKEW_STATUS	0x7ee06064	RW
APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL	0x7ee06068	RW
APHY_CSR_ADDR_PAD_MISC_CTRL	0x7ee0606c	RW
APHY_CSR_ADDR_PVT_COMP_CTRL	0x7ee06070	RW
APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL	0x7ee06074	RW
APHY_CSR_ADDR_PVT_COMP_STATUS	0x7ee06078	RW
APHY_CSR_ADDR_PVT_COMP_DEBUG	0x7ee0607c	RW
APHY_CSR_PHY_BIST_CNTRL_SPR	0x7ee06080	RW
APHY_CSR_PHY_BIST_CA_CRC_SPR	0x7ee06084	RW
APHY_CSR_ADDR_SPR0_RW	0x7ee06088	RW
APHY_CSR_ADDR_SPR1_RO	0x7ee0608c	RW
APHY_CSR_ADDR_SPR_RO	0x7ee06090	RW

ARM

Info

base	0x7E00B000

Registers

register name	address	type
ARM_CONTROL0	0x7e00b000	RW
ARM_ID_SECURE	0x7e00b00c	RW
ARM_TRANSLATE	0x7e00b100	RW
ARM_IRQ_PEND0	0x7e00b200	RW
ARM_IRQ_PEND1	0x7e00b204	RW
ARM_IRQ_PEND2	0x7e00b208	RW
ARM_IRQ_FAST	0x7e00b20c	RW
ARM_IRQ_ENBL1	0x7e00b210	RW
ARM_IRQ_ENBL2	0x7e00b214	RW
ARM_IRQ_ENBL3	0x7e00b218	RW
ARM_IRQ_DIBL1	0x7e00b21c	RW
ARM_IRQ_DIBL2	0x7e00b220	RW
ARM_IRQ_DIBL3	0x7e00b224	RW
ARM_T_LOAD	0x7e00b400	RW
ARM_T_VALUE	0x7e00b404	RW
ARM_T_CONTROL	0x7e00b408	RW
ARM_T_IRQCNTL	0x7e00b40c	RW
ARM_T_RAWIRQ	0x7e00b410	RW
ARM_T_MSKIRQ	0x7e00b414	RW
ARM_T_RELOAD	0x7e00b418	RW
ARM_T_PREDIV	0x7e00b41c	RW
ARM_T_FREECNT	0x7e00b420	RW
ARM_CONTROL1	0x7e00b440	RW
ARM_STATUS	0x7e00b444	RW
ARM_ERRHALT	0x7e00b448	RW
ARM_ID	0x7e00b44c	RW
ARM_0_SEM0	0x7e00b800	RW
ARM_0_SEMS	0x7e00b800	RW
ARM_0_SEM1	0x7e00b804	RW
ARM_0_SEM2	0x7e00b808	RW
ARM_0_SEM3	0x7e00b80c	RW
ARM_0_SEM4	0x7e00b810	RW
ARM_0_SEM5	0x7e00b814	RW
ARM_0_SEM6	0x7e00b818	RW
ARM_0_SEM7	0x7e00b81c	RW
ARM_0_BELL0	0x7e00b840	RW
ARM_0_BELL1	0x7e00b844	RW
ARM_0_BELL2	0x7e00b848	RW
ARM_0_BELL3	0x7e00b84c	RW
ARM_0_MAIL0_RD	0x7e00b880	RW
ARM_0_MAIL0_WRT	0x7e00b880	RW
ARM_0_MAIL0_POL	0x7e00b890	RW
ARM_0_MAIL0_SND	0x7e00b894	RW
ARM_0_MAIL0_STA	0x7e00b898	RW
ARM_0_MAIL0_CNF	0x7e00b89c	RW
ARM_0_MAIL1_WRT	0x7e00b8a0	RW
ARM_0_MAIL1_STA	0x7e00b8b8	RW
ARM_0_SEMCLRDBG	0x7e00b8e0	RW
ARM_0_BELLCLRDBG	0x7e00b8e4	RW
ARM_0_ALL_IRQS	0x7e00b8f8	RW
ARM_0_MY_IRQS	0x7e00b8fc	RW
ARM_1_SEM0	0x7e00b900	RW
ARM_1_SEMS	0x7e00b900	RW
ARM_1_SEM1	0x7e00b904	RW
ARM_1_SEM2	0x7e00b908	RW
ARM_1_SEM3	0x7e00b90c	RW
ARM_1_SEM4	0x7e00b910	RW
ARM_1_SEM5	0x7e00b914	RW
ARM_1_SEM6	0x7e00b918	RW
ARM_1_SEM7	0x7e00b91c	RW
ARM_1_BELL0	0x7e00b940	RW
ARM_1_BELL1	0x7e00b944	RW
ARM_1_BELL2	0x7e00b948	RW
ARM_1_BELL3	0x7e00b94c	RW
ARM_1_MAIL0_WRT	0x7e00b980	RW
ARM_1_MAIL0_STA	0x7e00b998	RW
ARM_1_MAIL1_WRT	0x7e00b9a0	RW
ARM_1_MAIL1_RD	0x7e00b9a0	RW
ARM_1_MAIL1_POL	0x7e00b9b0	RW
ARM_1_MAIL1_SND	0x7e00b9b4	RW
ARM_1_MAIL1_STA	0x7e00b9b8	RW
ARM_1_MAIL1_CNF	0x7e00b9bc	RW
ARM_1_SEMCLRDBG	0x7e00b9e0	RW
ARM_1_BELLCLRDBG	0x7e00b9e4	RW
ARM_1_ALL_IRQS	0x7e00b9f8	RW
ARM_1_MY_IRQS	0x7e00b9fc	RW
ARM_2_SEM0	0x7e00ba00	RW
ARM_2_SEMS	0x7e00ba00	RW
ARM_2_SEM1	0x7e00ba04	RW
ARM_2_SEM2	0x7e00ba08	RW
ARM_2_SEM3	0x7e00ba0c	RW
ARM_2_SEM4	0x7e00ba10	RW
ARM_2_SEM5	0x7e00ba14	RW
ARM_2_SEM6	0x7e00ba18	RW
ARM_2_SEM7	0x7e00ba1c	RW
ARM_2_BELL0	0x7e00ba40	RW
ARM_2_BELL1	0x7e00ba44	RW
ARM_2_BELL2	0x7e00ba48	RW
ARM_2_BELL3	0x7e00ba4c	RW
ARM_2_MAIL0_WRT	0x7e00ba80	RW
ARM_2_MAIL0_STA	0x7e00ba98	RW
ARM_2_MAIL1_WRT	0x7e00baa0	RW
ARM_2_MAIL1_STA	0x7e00bab8	RW
ARM_2_SEMCLRDBG	0x7e00bae0	RW
ARM_2_BELLCLRDBG	0x7e00bae4	RW
ARM_2_ALL_IRQS	0x7e00baf8	RW
ARM_2_MY_IRQS	0x7e00bafc	RW
ARM_3_SEM0	0x7e00bb00	RW
ARM_3_SEMS	0x7e00bb00	RW
ARM_3_SEM1	0x7e00bb04	RW
ARM_3_SEM2	0x7e00bb08	RW
ARM_3_SEM3	0x7e00bb0c	RW
ARM_3_SEM4	0x7e00bb10	RW
ARM_3_SEM5	0x7e00bb14	RW
ARM_3_SEM6	0x7e00bb18	RW
ARM_3_SEM7	0x7e00bb1c	RW
ARM_3_BELL0	0x7e00bb40	RW
ARM_3_BELL1	0x7e00bb44	RW
ARM_3_BELL2	0x7e00bb48	RW
ARM_3_BELL3	0x7e00bb4c	RW
ARM_3_MAIL0_WRT	0x7e00bb80	RW
ARM_3_MAIL0_STA	0x7e00bb98	RW
ARM_3_MAIL1_WRT	0x7e00bba0	RW
ARM_3_MAIL1_STA	0x7e00bbb8	RW
ARM_3_SEMCLRDBG	0x7e00bbe0	RW
ARM_3_BELLCLRDBG	0x7e00bbe4	RW
ARM_3_ALL_IRQS	0x7e00bbf8	RW
ARM_3_MY_IRQS	0x7e00bbfc	RW

Unsupported defines

define	value
ARM_AIS0_HAVEDATA	0x00000010
ARM_AIS0_HAVESPAC	0x00000020
ARM_AIS0_OPPEMPTY	0x00000040
ARM_AIS1_HAVEDATA	0x00000080
ARM_AIS1_HAVESPAC	0x00000100
ARM_AIS1_OPPEMPTY	0x00000200
ARM_AIS_BELL0	0x00000001
ARM_AIS_BELL1	0x00000002
ARM_AIS_BELL2	0x00000004
ARM_AIS_BELL3	0x00000008
ARM_BD_BELL0	0x00000100
ARM_BD_BELL1	0x00000200
ARM_BD_BELL2	0x00000400
ARM_BD_BELL3	0x00000800
ARM_BD_OWN0	0x00000003
ARM_BD_OWN1	0x0000000C
ARM_BD_OWN2	0x00000030
ARM_BD_OWN3	0x000000C0
ARM_C0_APROTMSK	0x0000F000
ARM_C0_APROTPASS	0x0000A000
ARM_C0_APROTSYST	0x0000F000
ARM_C0_APROTUSER	0x00000000
ARM_C0_BOOTHI	0x00000010
ARM_C0_BRESP0	0x00000000
ARM_C0_BRESP1	0x00000004
ARM_C0_BRESP2	0x00000008
ARM_C0_DBG0SYNC	0x00010000
ARM_C0_DBG1SYNC	0x00020000
ARM_C0_FULLPERI	0x00000040
ARM_C0_JTAGBASH	0x00000800
ARM_C0_JTAGGPIO	0x00000C00
ARM_C0_JTAGMASK	0x00000E00
ARM_C0_JTAGOFF	0x00000000
ARM_C0_PASSHALT	0x00080000
ARM_C0_PRIO_L2	0x0F000000
ARM_C0_PRIO_PER	0x00F00000
ARM_C0_PRIO_UC	0xF0000000
ARM_C0_SIZ128M	0x00000000
ARM_C0_SIZ1G	0x00000003
ARM_C0_SIZ256M	0x00000001
ARM_C0_SIZ512M	0x00000002
ARM_C0_SWDBGREQ	0x00040000
ARM_C0_UNUSED05	0x00000020
ARM_C0_UNUSED78	0x00000180
ARM_C1_BELL0	0x00000004
ARM_C1_BELL1	0x00000008
ARM_C1_MAIL	0x00000002
ARM_C1_PERSON	0x00000100
ARM_C1_REQSTOP	0x00000200
ARM_C1_TIMER	0x00000001
ARM_DS_ACTIVE	0x00000004
ARM_DS_OWNER	0x00000003
ARM_EH_ARMHALT	0x00000020
ARM_EH_ILLADDRS1	0x00000002
ARM_EH_ILLADDRS2	0x00000004
ARM_EH_PERIBURST	0x00000001
ARM_EH_VPU0HALT	0x00000008
ARM_EH_VPU1HALT	0x00000010
ARM_I0_BANK1	0x00000100
ARM_I0_BANK2	0x00000200
ARM_I0_BELL0	0x00000004
ARM_I0_BELL1	0x00000008
ARM_I0_MAIL	0x00000002
ARM_I0_TIMER	0x00000001
ARM_IDVAL	0x364D5241
ARM_IE_BELL0	0x00000004
ARM_IE_BELL1	0x00000008
ARM_IE_ILLEGAL	0x00000040
ARM_IE_MAIL	0x00000002
ARM_IE_TIMER	0x00000001
ARM_IE_VP0HALT	0x00000010
ARM_IE_VP1HALT	0x00000020
ARM_IF_BELL0	0x00000042
ARM_IF_BELL1	0x00000043
ARM_IF_ENABLE	0x00000080
ARM_IF_ILLEGAL	0x00000046
ARM_IF_INDEX	0x0000007F
ARM_IF_MAIL	0x00000041
ARM_IF_TIMER	0x00000040
ARM_IF_VCMASK	0x0000003F
ARM_IF_VP0HALT	0x00000044
ARM_IF_VP1HALT	0x00000045
ARM_MC_ERRNOOWN	0x00000100
ARM_MC_ERROVERFLW	0x00000200
ARM_MC_ERRUNDRFLW	0x00000400
ARM_MC_IHAVEDATAIRQEN	0x00000001
ARM_MC_IHAVEDATAIRQPEND	0x00000010
ARM_MC_IHAVESPACEIRQEN	0x00000002
ARM_MC_IHAVESPACEIRQPEND	0x00000020
ARM_MC_MAIL_CLEAR	0x00000008
ARM_MC_OPPISEMPTYIRQEN	0x00000004
ARM_MC_OPPISEMPTYIRQPEND	0x00000040
ARM_MS_EMPTY	0x40000000
ARM_MS_FULL	0x80000000
ARM_MS_LEVEL	0x400000FF
ARM_MYIRQ_BELL	0x00000001
ARM_MYIRQ_MAIL	0x00000002
ARM_SBM_OWN0	0x7e00b800
ARM_SBM_OWN1	0x7e00b900
ARM_SBM_OWN2	0x7e00ba00
ARM_SBM_OWN3	0x7e00bb00
ARM_SD_OWN0	0x00000003
ARM_SD_OWN1	0x0000000C
ARM_SD_OWN2	0x00000030
ARM_SD_OWN3	0x000000C0
ARM_SD_OWN4	0x00000300
ARM_SD_OWN5	0x00000C00
ARM_SD_OWN6	0x00003000
ARM_SD_OWN7	0x0000C000
ARM_SD_SEM0	0x00010000
ARM_SD_SEM1	0x00020000
ARM_SD_SEM2	0x00040000
ARM_SD_SEM3	0x00080000
ARM_SD_SEM4	0x00100000
ARM_SD_SEM5	0x00200000
ARM_SD_SEM6	0x00400000
ARM_SD_SEM7	0x00800000
ARM_S_ACKSTOP	0x80000000
ARM_S_READPEND	0x000003FF
ARM_S_WRITPEND	0x000FFC00

ASB

Info

base	0x7e00a000
id	0x62726467

Registers

register name	address	type	width	mask	reset
ASB_AXI_BRDG_VERSION	0x7e00a000	RW	8	0x000000ff	0000000000
ASB_CPR_CTRL	0x7e00a004	RW	24	0x00ffffff	0x00000007
ASB_V3D_S_CTRL	0x7e00a008	RW	24	0x00ffffff	0x00000007
ASB_V3D_M_CTRL	0x7e00a00c	RW	24	0x00ffffff	0x00000007
ASB_ISP_S_CTRL	0x7e00a010	RW	24	0x00ffffff	0x00000007
ASB_ISP_M_CTRL	0x7e00a014	RW	24	0x00ffffff	0x00000007
ASB_H264_S_CTRL	0x7e00a018	RW	24	0x00ffffff	0x00000007
ASB_H264_M_CTRL	0x7e00a01c	RW	24	0x00ffffff	0x00000007

Register:ASB_CPR_CTRL (0x7e00a004)

field_name	start_bit	end_bit	set	clear	reset
ASB_CPR_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_CPR_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_CPR_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_CPR_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_CPR_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_CPR_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_V3D_S_CTRL (0x7e00a008)

field_name	start_bit	end_bit	set	clear	reset
ASB_V3D_S_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_V3D_S_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_V3D_S_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_V3D_S_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_V3D_S_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_V3D_S_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_V3D_M_CTRL (0x7e00a00c)

field_name	start_bit	end_bit	set	clear	reset
ASB_V3D_M_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_V3D_M_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_V3D_M_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_V3D_M_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_V3D_M_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_V3D_M_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_ISP_S_CTRL (0x7e00a010)

field_name	start_bit	end_bit	set	clear	reset
ASB_ISP_S_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_ISP_S_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_ISP_S_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_ISP_S_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_ISP_S_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_ISP_S_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_ISP_M_CTRL (0x7e00a014)

field_name	start_bit	end_bit	set	clear	reset
ASB_ISP_M_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_ISP_M_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_ISP_M_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_ISP_M_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_ISP_M_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_ISP_M_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_H264_S_CTRL (0x7e00a018)

field_name	start_bit	end_bit	set	clear	reset
ASB_H264_S_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_H264_S_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_H264_S_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_H264_S_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_H264_S_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_H264_S_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

Register:ASB_H264_M_CTRL (0x7e00a01c)

field_name	start_bit	end_bit	set	clear	reset
ASB_H264_M_CTRL_CLR_REQ	0	0	0x00000001	0xfffffffe	0x1
ASB_H264_M_CTRL_CLR_ACK	1	1	0x00000002	0xfffffffd	0x1
ASB_H264_M_CTRL_EMPTY	2	2	0x00000004	0xfffffffb	0x1
ASB_H264_M_CTRL_FULL	3	3	0x00000008	0xfffffff7	0x0
ASB_H264_M_CTRL_RCOUNT	4	13	0x00003ff0	0xffffc00f	0x0
ASB_H264_M_CTRL_WCOUNT	14	23	0x00ffc000	0xff003fff	0x0

AUX

Info

base	0x7E215000

Registers

register name	address	type
AUX_MU_IO	0x7e215040	MU_IO
AUX_MU_BDLS	0x7e215040	MU_BDLS
AUX_MU_BDMS	0x7e215044	MU_BDMS
AUX_MU_IER	0x7e215044	MU_IER
AUX_MU_IIR	0x7e215048	MU_IIR
AUX_MU_FCR	0x7e215048	MU_FCR
AUX_MU_LCR	0x7e21504c	MU_LCR
AUX_MU_MCR	0x7e215050	MU_MCR
AUX_MU_LSR	0x7e215054	MU_LSR
AUX_MU_MSR	0x7e215058	MU_MSR
AUX_MU_CNTL	0x7e215060	MU_CNTL
AUX_MU_STAT	0x7e215064	MU_STAT
AUX_MU_BAUD	0x7e215068	MU_BAUD
AUX_SPI0_CNTL0	0x7e215080	SPI0_CNTL0
AUX_SPI0_CNTL1	0x7e215084	SPI0_CNTL1
AUX_SPI0_STAT	0x7e215088	SPI0_STAT
AUX_SPI0_PEEK	0x7e21508c	SPI0_PEEK
AUX_SPI0_IO	0x7e2150a0	SPI0_IO
AUX_SPI0_TXHOLD	0x7e2150b0	SPI0_TXHOLD
AUX_SPI1_CNTL0	0x7e2150c0	SPI1_CNTL0
AUX_SPI1_CNTL1	0x7e2150c4	SPI1_CNTL1
AUX_SPI1_STAT	0x7e2150c8	SPI1_STAT
AUX_SPI1_PEEK	0x7e2150cc	SPI1_PEEK
AUX_SPI1_IO	0x7e2150e0	SPI1_IO
AUX_SPI1_TXHOLD	0x7e2150f0	SPI1_TXHOLD

Unsupported defines

define	value
AUX_ENABLES	0x7e215004
AUX_ENABLE_MINIUART	0x01
AUX_ENABLE_SPI0	0x02
AUX_ENABLE_SPI1	0x04
AUX_IO_BASE	0x7E215000
AUX_IRQ	0x7e215000
AUX_MU_CNTL_AUCTSINV	0x80
AUX_MU_CNTL_AURTRINV	0x40
AUX_MU_CNTL_AUTO_CTS	0x08
AUX_MU_CNTL_AUTO_RTR	0x04
AUX_MU_CNTL_FLOW1	0x20
AUX_MU_CNTL_FLOW2	0x10
AUX_MU_CNTL_FLOW3	0x00
AUX_MU_CNTL_FLOW4	0x30
AUX_MU_CNTL_REC_ENBL	0x01
AUX_MU_CNTL_TRN_ENBL	0x02
AUX_MU_FCR_RXCLR	0x02
AUX_MU_FCR_TXCLR	0x04
AUX_MU_IER_RXIRQEN	0x01
AUX_MU_IER_TXIRQEN	0x02
AUX_MU_IIR_IRQ	0x06
AUX_MU_IIR_NOIRQS	0x01
AUX_MU_LCR_7BITS	0x02
AUX_MU_LCR_8BITS	0x03
AUX_MU_LCR_BREAK	0x40
AUX_MU_LCR_DLAB	0x80
AUX_MU_LSR_DR	0x01
AUX_MU_LSR_OE	0x02
AUX_MU_LSR_TEMT	0x40
AUX_MU_LSR_THRE	0x20
AUX_MU_MCR_RTS	0x02
AUX_MU_MSR_CTS	0x10
AUX_MU_SCRATCH	0x7e21505c
AUX_MU_STAT_CTS	0x00000080
AUX_MU_STAT_RTR	0x00000040
AUX_MU_STAT_RXFILL	0x00FF0000
AUX_MU_STAT_RX_DATA	0x00000001
AUX_MU_STAT_RX_IDLE	0x00000004
AUX_MU_STAT_RX_OFLW	0x00000010
AUX_MU_STAT_TXDONE	0x00000200
AUX_MU_STAT_TXEMPTY	0x00000100
AUX_MU_STAT_TXFILL	0xFF000000
AUX_MU_STAT_TX_FULL	0x00000020
AUX_MU_STAT_TX_IDLE	0x00000008
AUX_MU_STAT_TX_SPACE	0x00000002
AUX_SPI_CNTL0_BITS	0x0000003F
AUX_SPI_CNTL0_CS0_N	0x000C0000
AUX_SPI_CNTL0_CS1_N	0x000A0000
AUX_SPI_CNTL0_CS2_N	0x00060000
AUX_SPI_CNTL0_CSA_N	0x00000000
AUX_SPI_CNTL0_CSFROMFF	0x00008000
AUX_SPI_CNTL0_CS_HIGH	0x000E0000
AUX_SPI_CNTL0_FFCLR	0x00000200
AUX_SPI_CNTL0_HOLD0	0x00000000
AUX_SPI_CNTL0_HOLD10	0x00003000
AUX_SPI_CNTL0_HOLD4	0x00001000
AUX_SPI_CNTL0_HOLD7	0x00002000
AUX_SPI_CNTL0_INFALL	0x00000000
AUX_SPI_CNTL0_INRISE	0x00000400
AUX_SPI_CNTL0_INVCLK	0x00000080
AUX_SPI_CNTL0_OUTFALL	0x00000000
AUX_SPI_CNTL0_OUTMS	0x00000040
AUX_SPI_CNTL0_OUTRISE	0x00000100
AUX_SPI_CNTL0_POSTIN	0x00010000
AUX_SPI_CNTL0_SERENBL	0x00000800
AUX_SPI_CNTL0_SPEED	0xFFF00000
AUX_SPI_CNTL0_SPEEDSHFT	20
AUX_SPI_CNTL0_VARWID	0x00004000
AUX_SPI_CNTL1_CSPLUS1	0x00000100
AUX_SPI_CNTL1_CSPLUS2	0x00000200
AUX_SPI_CNTL1_CSPLUS3	0x00000300
AUX_SPI_CNTL1_CSPLUS4	0x00000400
AUX_SPI_CNTL1_CSPLUS5	0x00000500
AUX_SPI_CNTL1_CSPLUS6	0x00000600
AUX_SPI_CNTL1_CSPLUS7	0x00000700
AUX_SPI_CNTL1_DONEIRQ	0x00000080
AUX_SPI_CNTL1_EMPTYIRQ	0x00000040
AUX_SPI_CNTL1_HOLDIN	0x00000001
AUX_SPI_CNTL1_INMS	0x00000002
AUX_SPI_STAT_BITCNT	0x0000003F
AUX_SPI_STAT_BUSY	0x00000040
AUX_SPI_STAT_RXEMPTY	0x00000080
AUX_SPI_STAT_RXFILL	0x000F0000
AUX_SPI_STAT_RXFULL	0x00000100
AUX_SPI_STAT_TXEMPTY	0x00000200
AUX_SPI_STAT_TXFILL	0x0F000000
AUX_SPI_STAT_TXFULL	0x00000400

AVE_IN

Info

base	0x7e910000
id	0x61766530

Registers

register name	address	type	width	mask	reset
AVE_IN_CTRL	0x7e910000	RW	32	0x87ffffff	0x08000080
AVE_IN_STATUS	0x7e910004	RW	32	0x9f733f7f	0000000000
AVE_IN_BUF0_ADDRESS	0x7e910008	RW	32	0xffffffff	0000000000
AVE_IN_BUF1_ADDRESS	0x7e91000c	RW	32	0xffffffff	0000000000
AVE_IN_MAX_TRANSFER	0x7e910010	RW	32	0xffffffff	0000000000
AVE_IN_LINE_LENGTH	0x7e910014	RW	12	0x00000fff	0000000000
AVE_IN_CURRENT_ADDRESS	0x7e910018	RW	32	0xffffffff	0000000000
AVE_IN_CURRENT_LINE_BUF0	0x7e91001c	RW	32	0x80000fff	0000000000
AVE_IN_CURRENT_LINE_BUF1	0x7e910020	RW	32	0x80000fff	0000000000
AVE_IN_CURRENT_LINE_NUM	0x7e910024	RW	32	0xe0000fff	0000000000
AVE_IN_OVERRUN_ADDRESS	0x7e910028	RW	32	0xffffffff	0000000000
AVE_IN_LINE_NUM_INT	0x7e91002c	RW	12	0x00000fff	0000000000
AVE_IN_CALC_LINE_STEP	0x7e910030	RW	12	0x00000fff	0000000000
AVE_IN_OUTSTANDING_BUFF0	0x7e910034	RW	8	0x000000ff	0000000000
AVE_IN_OUTSTANDING_BUFF1	0x7e910038	RW	8	0x000000ff	0000000000
AVE_IN_CHAR_CTRL	0x7e91003c	RW	32	0x8000000f	0000000000
AVE_IN_SYNC_CTRL	0x7e910040	RW	8	0x0000008f	0000000000
AVE_IN_FRAME_NUM	0x7e910044	RW	12	0x00000fff	0000000000
AVE_IN_BLOCK_ID	0x7e910060	RW	32	0xffffffff	0x61766530

Register:AVE_IN_CTRL (0x7e910000)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CTRL_OVERRUN_IRQ_EN	0	0	0x00000001	0xfffffffe	0x0
AVE_IN_CTRL_BUF0_IRQ_EN	1	1	0x00000002	0xfffffffd	0x0
AVE_IN_CTRL_BUF1_IRQ_EN	2	2	0x00000004	0xfffffffb	0x0
AVE_IN_CTRL_BUF_SER_IRQ_EN	3	3	0x00000008	0xfffffff7	0x0
AVE_IN_CTRL_LINE_IRQ_EN	4	4	0x00000010	0xffffffef	0x0
AVE_IN_CTRL_HSYNC_IRQ_EN	5	5	0x00000020	0xffffffdf	0x0
AVE_IN_CTRL_FRAME_RATE_IRQ_EN	6	6	0x00000040	0xffffffbf	0x0
AVE_IN_CTRL_PRIV_MODE	7	7	0x00000080	0xffffff7f	0x1
AVE_IN_CTRL_LENGTH_IN_PXLS	8	8	0x00000100	0xfffffeff	0x0
AVE_IN_CTRL_FRAME_MODE	9	10	0x00000600	0xfffff9ff	0x0
AVE_IN_CTRL_BYTE_ORDER	11	13	0x00003800	0xffffc7ff	0x0
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT	14	14	0x00004000	0xffffbfff	0x0
AVE_IN_CTRL_EN_OVERRUN_ABORT	15	15	0x00008000	0xffff7fff	0x0
AVE_IN_CTRL_LOW_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
AVE_IN_CTRL_HIGH_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
AVE_IN_CTRL_PRIORITY_LIMIT	24	26	0x07000000	0xf8ffffff	0x0
missing definiton	27	30	NA	NA	NA
AVE_IN_CTRL_ENABLE	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_IN_STATUS (0x7e910004)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_STATUS_OVERRUN_DET	0	0	0x00000001	0xfffffffe	0x0
AVE_IN_STATUS_BUF0_COMPL	1	1	0x00000002	0xfffffffd	0x0
AVE_IN_STATUS_BUF1_COMPL	2	2	0x00000004	0xfffffffb	0x0
AVE_IN_STATUS_BUF_NOT_SERV	3	3	0x00000008	0xfffffff7	0x0
AVE_IN_STATUS_LINE_NUM_HIT	4	4	0x00000010	0xffffffef	0x0
AVE_IN_STATUS_HSYNC_DET	5	5	0x00000020	0xffffffdf	0x0
AVE_IN_STATUS_FRAME_RATE_DET	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
AVE_IN_STATUS_FRAME_RATE	8	9	0x00000300	0xfffffcff	0x0
AVE_IN_STATUS_INTERLACED	10	10	0x00000400	0xfffffbff	0x0
AVE_IN_STATUS_EVEN_FIELD	11	11	0x00000800	0xfffff7ff	0x0
AVE_IN_STATUS_VFORM_FIELD	12	12	0x00001000	0xffffefff	0x0
AVE_IN_STATUS_CSYNC_FIELD	13	13	0x00002000	0xffffdfff	0x0
missing definiton	14	15	NA	NA	NA
AVE_IN_STATUS_MAX_HIT	16	16	0x00010000	0xfffeffff	0x0
AVE_IN_STATUS_CURRENT_BUF	17	17	0x00020000	0xfffdffff	0x0
missing definiton	18	19	NA	NA	NA
AVE_IN_STATUS_AXI_STATE	20	22	0x00700000	0xff8fffff	0x0
missing definiton	23	23	NA	NA	NA
AVE_IN_STATUS_OVERRUN_CNT	24	28	0x1f000000	0xe0ffffff	0x0
missing definiton	29	30	NA	NA	NA
AVE_IN_STATUS_CAPTURING	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_IN_BUF0_ADDRESS (0x7e910008)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_BUF0_ADDRESS_BUF0_ADDR	0	31	0xffffffff	0x00000000	0x0

Register:AVE_IN_BUF1_ADDRESS (0x7e91000c)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_BUF1_ADDRESS_BUF1_ADDR	0	31	0xffffffff	0x00000000	0x0

Register:AVE_IN_MAX_TRANSFER (0x7e910010)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_MAX_TRANSFER_MAX_TRANSFER	0	31	0xffffffff	0x00000000	0x0

Register:AVE_IN_LINE_LENGTH (0x7e910014)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_LINE_LENGTH_LINE_LENGTH	0	11	0x00000fff	0xfffff000	0x0

Register:AVE_IN_CURRENT_ADDRESS (0x7e910018)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CURRENT_ADDRESS_CUR_ADDR	0	31	0xffffffff	0x00000000	0x0

Register:AVE_IN_CURRENT_LINE_BUF0 (0x7e91001c)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE	0	11	0x00000fff	0xfffff000	0x0
missing definiton	12	30	NA	NA	NA
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_IN_CURRENT_LINE_BUF1 (0x7e910020)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE	0	11	0x00000fff	0xfffff000	0x0
missing definiton	12	30	NA	NA	NA
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_IN_CURRENT_LINE_NUM (0x7e910024)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE	0	11	0x00000fff	0xfffff000	0x0
missing definiton	12	28	NA	NA	NA
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER	29	29	0x20000000	0xdfffffff	0x0
AVE_IN_CURRENT_LINE_NUM_INTERLACED	30	30	0x40000000	0xbfffffff	0x0
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_IN_OVERRUN_ADDRESS (0x7e910028)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR	0	31	0xffffffff	0x00000000	0x0

Register:AVE_IN_LINE_NUM_INT (0x7e91002c)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_LINE_NUM_INT_LINE_NUM_INT	0	11	0x00000fff	0xfffff000	0x0

Register:AVE_IN_CALC_LINE_STEP (0x7e910030)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP	0	11	0x00000fff	0xfffff000	0x0

Register:AVE_IN_FRAME_NUM (0x7e910044)

field_name	start_bit	end_bit	set	clear	reset
AVE_IN_FRAME_NUM_FRAME_NUM	0	11	0x00000fff	0xfffff000	0x0

AVE_OUT

Info

base	0x7e240000
id	0x61766538

Registers

register name	address	type	width	mask	reset
AVE_OUT_CTRL	0x7e240000	RW	32	0xc0fff13f	0x40000100
AVE_OUT_STATUS	0x7e240004	RW	10	0x000003f7	0000000000
AVE_OUT_OFFSET	0x7e240008	RW	32	0x80ffffff	0x80109090
AVE_OUT_Y_COEFF	0x7e24000c	RW	30	0x3fffffff	0x0994b43a
AVE_OUT_CB_COEFF	0x7e240010	RW	30	0x3fffffff	0x3a9d5900
AVE_OUT_CR_COEFF	0x7e240014	RW	30	0x3fffffff	0x100ca7d6
AVE_OUT_BLOCK_ID	0x7e240060	RW	32	0xffffffff	0x61766538

Register:AVE_OUT_CTRL (0x7e240000)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_CTRL_ERROR_IRQ_EN	0	0	0x00000001	0xfffffffe	0x0
AVE_OUT_CTRL_COEFF_IRQ_EN	1	1	0x00000002	0xfffffffd	0x0
AVE_OUT_CTRL_REFRESH_RATE	2	3	0x0000000c	0xfffffff3	0x0
AVE_OUT_CTRL_MODE	4	5	0x00000030	0xffffffcf	0x0
missing definiton	6	7	NA	NA	NA
AVE_OUT_CTRL_PRIV_ACCESS	8	8	0x00000100	0xfffffeff	0x1
missing definiton	9	11	NA	NA	NA
AVE_OUT_CTRL_INTERLEAVE	12	12	0x00001000	0xffffefff	0x0
AVE_OUT_CTRL_NTSC_PAL_IDENT	13	13	0x00002000	0xffffdfff	0x0
AVE_OUT_CTRL_INVERT_HSYNC	14	14	0x00004000	0xffffbfff	0x0
AVE_OUT_CTRL_INVERT_VSYNC	15	15	0x00008000	0xffff7fff	0x0
AVE_OUT_CTRL_INVERT_EVEN_FIELD	16	16	0x00010000	0xfffeffff	0x0
AVE_OUT_CTRL_INVERT_CSYNC	17	17	0x00020000	0xfffdffff	0x0
AVE_OUT_CTRL_INVERT_DSYNC	18	18	0x00040000	0xfffbffff	0x0
AVE_OUT_CTRL_BYTE_SWAP	19	23	0x00f80000	0xff07ffff	0x0
missing definiton	24	29	NA	NA	NA
AVE_OUT_CTRL_SOFT_RESET	30	30	0x40000000	0xbfffffff	0x1
AVE_OUT_CTRL_ENABLE	31	31	0x80000000	0x7fffffff	0x0

Register:AVE_OUT_STATUS (0x7e240004)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_STATUS_PXL_FORMAT_ERROR	0	0	0x00000001	0xfffffffe	0x0
AVE_OUT_STATUS_PXL_OUTPUT_ERROR	1	1	0x00000002	0xfffffffd	0x0
AVE_OUT_STATUS_COEFF_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
AVE_OUT_STATUS_HFRONT_PORCH	4	4	0x00000010	0xffffffef	0x0
AVE_OUT_STATUS_HBACK_PORCH	5	5	0x00000020	0xffffffdf	0x0
AVE_OUT_STATUS_HSYNC	6	6	0x00000040	0xffffffbf	0x0
AVE_OUT_STATUS_VFRONT_PORCH	7	7	0x00000080	0xffffff7f	0x0
AVE_OUT_STATUS_VBACK_PORCH	8	8	0x00000100	0xfffffeff	0x0
AVE_OUT_STATUS_VSYNC	9	9	0x00000200	0xfffffdff	0x0

Register:AVE_OUT_OFFSET (0x7e240008)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_OFFSET_BLUE_OFFSET	0	7	0x000000ff	0xffffff00	0x90
AVE_OUT_OFFSET_GREEN_OFFSET	8	15	0x0000ff00	0xffff00ff	0x90
AVE_OUT_OFFSET_RED_OFFSET	16	23	0x00ff0000	0xff00ffff	0x10
missing definiton	24	30	NA	NA	NA
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING	31	31	0x80000000	0x7fffffff	0x1

Register:AVE_OUT_Y_COEFF (0x7e24000c)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_Y_COEFF_BLUE_COEFF	0	9	0x000003ff	0xfffffc00	0x3a
AVE_OUT_Y_COEFF_GREEN_COEFF	10	19	0x000ffc00	0xfff003ff	0x12d
AVE_OUT_Y_COEFF_RED_COEFF	20	29	0x3ff00000	0xc00fffff	0x99

Register:AVE_OUT_CB_COEFF (0x7e240010)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_CB_COEFF_BLUE_COEFF	0	9	0x000003ff	0xfffffc00	0x100
AVE_OUT_CB_COEFF_GREEN_COEFF	10	19	0x000ffc00	0xfff003ff	0x356
AVE_OUT_CB_COEFF_RED_COEFF	20	29	0x3ff00000	0xc00fffff	0x3a9

Register:AVE_OUT_CR_COEFF (0x7e240014)

field_name	start_bit	end_bit	set	clear	reset
AVE_OUT_CR_COEFF_BLUE_COEFF	0	9	0x000003ff	0xfffffc00	0x3d6
AVE_OUT_CR_COEFF_GREEN_COEFF	10	19	0x000ffc00	0xfff003ff	0x329
AVE_OUT_CR_COEFF_RED_COEFF	20	29	0x3ff00000	0xc00fffff	0x100

CAM0

Info

base	0x7e800000
id	0x7563616d

Registers

register name	address	type	width	mask	reset
CAM0_CAMCTL	0x7e800000	RW	32	0xffffffff	0000000000
CAM0_CAMSTA	0x7e800004	RW	32	0xffffffff	0000000000
CAM0_CAMANA	0x7e800008	RW	32	0xffffffff	0x00000777
CAM0_CAMPRI	0x7e80000c	RW	32	0xffffffff	0000000000
CAM0_CAMCLK	0x7e800010	RW	32	0xffffffff	0x00000002
CAM0_CAMCLT	0x7e800014	RW	32	0xffffffff	0000000000
CAM0_CAMDAT0	0x7e800018	RW	32	0xffffffff	0x00000002
CAM0_CAMDAT1	0x7e80001c	RW	32	0xffffffff	0x00000002
CAM0_CAMDAT2	0x7e800020	RW	32	0xffffffff	0x00000002
CAM0_CAMDAT3	0x7e800024	RW	32	0xffffffff	0x00000002
CAM0_CAMDLT	0x7e800028	RW	32	0xffffffff	0000000000
CAM0_CAMCMP0	0x7e80002c	RW	32	0xffffffff	0000000000
CAM0_CAMCMP1	0x7e800030	RW	32	0xffffffff	0000000000
CAM0_CAMCAP0	0x7e800034	RW	32	0xffffffff	0000000000
CAM0_CAMCAP1	0x7e800038	RW	32	0xffffffff	0000000000
CAM0_CAMDBG0	0x7e8000f0	RW	32	0xffffffff	0000000000
CAM0_CAMDBG1	0x7e8000f4	RW	32	0xffffffff	0000000000
CAM0_CAMDBG2	0x7e8000f8	RW	32	0xffffffff	0000000000
CAM0_CAMDBG3	0x7e8000fc	RW	32	0xffffffff	0000000000
CAM0_CAMICTL	0x7e800100	RW	32	0xffffffff	0000000000
CAM0_CAMISTA	0x7e800104	RW	32	0xffffffff	0000000000
CAM0_CAMIDI0	0x7e800108	RW	32	0xffffffff	0000000000
CAM0_CAMIPIPE	0x7e80010c	RW	32	0xffffffff	0000000000
CAM0_CAMIBSA0	0x7e800110	RW	32	0xffffffff	0000000000
CAM0_CAMIBEA0	0x7e800114	RW	32	0xffffffff	0000000000
CAM0_CAMIBLS	0x7e800118	RW	32	0xffffffff	0000000000
CAM0_CAMIBWP	0x7e80011c	RW	32	0xffffffff	0000000000
CAM0_CAMIHWIN	0x7e800120	RW	32	0xffffffff	0000000000
CAM0_CAMIHSTA	0x7e800124	RW	32	0xffffffff	0000000000
CAM0_CAMIVWIN	0x7e800128	RW	32	0xffffffff	0000000000
CAM0_CAMIVSTA	0x7e80012c	RW	32	0xffffffff	0000000000
CAM0_CAMICC	0x7e800130	RW	32	0xffffffff	0000000000
CAM0_CAMICS	0x7e800134	RW	32	0xffffffff	0000000000
CAM0_CAMIDC	0x7e800138	RW	32	0xffffffff	0000000000
CAM0_CAMIDPO	0x7e80013c	RW	32	0xffffffff	0000000000
CAM0_CAMIDCA	0x7e800140	RW	32	0xffffffff	0000000000
CAM0_CAMIDCD	0x7e800144	RW	32	0xffffffff	0000000000
CAM0_CAMIDS	0x7e800148	RW	32	0xffffffff	0000000000
CAM0_CAMDCS	0x7e800200	RW	32	0xffffffff	0000000000
CAM0_CAMDBSA0	0x7e800204	RW	32	0xffffffff	0000000000
CAM0_CAMDBEA0	0x7e800208	RW	32	0xffffffff	0000000000
CAM0_CAMDBWP	0x7e80020c	RW	32	0xffffffff	0000000000
CAM0_CAMDBCTL	0x7e800300	RW	32	0xffffffff	0000000000
CAM0_CAMIBSA1	0x7e800304	RW	32	0xffffffff	0000000000
CAM0_CAMIBEA1	0x7e800308	RW	32	0xffffffff	0000000000
CAM0_CAMIDI1	0x7e80030c	RW	32	0xffffffff	0000000000
CAM0_CAMDBSA1	0x7e800310	RW	32	0xffffffff	0000000000
CAM0_CAMDBEA1	0x7e800314	RW	32	0xffffffff	0000000000
CAM0_CAMMISC	0x7e800400	RW	32	0xffffffff	0000000000

CAM1

Info

base	0x7e801000
id	0x7563616d

Registers

register name	address	type	width	mask	reset
CAM1_CAMCTL	0x7e801000	RW	32	0xffffffff	0000000000
CAM1_CAMSTA	0x7e801004	RW	32	0xffffffff	0000000000
CAM1_CAMANA	0x7e801008	RW	32	0xffffffff	0x00000777
CAM1_CAMPRI	0x7e80100c	RW	32	0xffffffff	0000000000
CAM1_CAMCLK	0x7e801010	RW	32	0xffffffff	0x00000002
CAM1_CAMCLT	0x7e801014	RW	32	0xffffffff	0000000000
CAM1_CAMDAT0	0x7e801018	RW	32	0xffffffff	0x00000002
CAM1_CAMDAT1	0x7e80101c	RW	32	0xffffffff	0x00000002
CAM1_CAMDAT2	0x7e801020	RW	32	0xffffffff	0x00000002
CAM1_CAMDAT3	0x7e801024	RW	32	0xffffffff	0x00000002
CAM1_CAMDLT	0x7e801028	RW	32	0xffffffff	0000000000
CAM1_CAMCMP0	0x7e80102c	RW	32	0xffffffff	0000000000
CAM1_CAMCMP1	0x7e801030	RW	32	0xffffffff	0000000000
CAM1_CAMCAP0	0x7e801034	RW	32	0xffffffff	0000000000
CAM1_CAMCAP1	0x7e801038	RW	32	0xffffffff	0000000000
CAM1_CAMDBG0	0x7e8010f0	RW	32	0xffffffff	0000000000
CAM1_CAMDBG1	0x7e8010f4	RW	32	0xffffffff	0000000000
CAM1_CAMDBG2	0x7e8010f8	RW	32	0xffffffff	0000000000
CAM1_CAMDBG3	0x7e8010fc	RW	32	0xffffffff	0000000000
CAM1_CAMICTL	0x7e801100	RW	32	0xffffffff	0000000000
CAM1_CAMISTA	0x7e801104	RW	32	0xffffffff	0000000000
CAM1_CAMIDI0	0x7e801108	RW	32	0xffffffff	0000000000
CAM1_CAMIPIPE	0x7e80110c	RW	32	0xffffffff	0000000000
CAM1_CAMIBSA0	0x7e801110	RW	32	0xffffffff	0000000000
CAM1_CAMIBEA0	0x7e801114	RW	32	0xffffffff	0000000000
CAM1_CAMIBLS	0x7e801118	RW	32	0xffffffff	0000000000
CAM1_CAMIBWP	0x7e80111c	RW	32	0xffffffff	0000000000
CAM1_CAMIHWIN	0x7e801120	RW	32	0xffffffff	0000000000
CAM1_CAMIHSTA	0x7e801124	RW	32	0xffffffff	0000000000
CAM1_CAMIVWIN	0x7e801128	RW	32	0xffffffff	0000000000
CAM1_CAMIVSTA	0x7e80112c	RW	32	0xffffffff	0000000000
CAM1_CAMICC	0x7e801130	RW	32	0xffffffff	0000000000
CAM1_CAMICS	0x7e801134	RW	32	0xffffffff	0000000000
CAM1_CAMIDC	0x7e801138	RW	32	0xffffffff	0000000000
CAM1_CAMIDPO	0x7e80113c	RW	32	0xffffffff	0000000000
CAM1_CAMIDCA	0x7e801140	RW	32	0xffffffff	0000000000
CAM1_CAMIDCD	0x7e801144	RW	32	0xffffffff	0000000000
CAM1_CAMIDS	0x7e801148	RW	32	0xffffffff	0000000000
CAM1_CAMDCS	0x7e801200	RW	32	0xffffffff	0000000000
CAM1_CAMDBSA0	0x7e801204	RW	32	0xffffffff	0000000000
CAM1_CAMDBEA0	0x7e801208	RW	32	0xffffffff	0000000000
CAM1_CAMDBWP	0x7e80120c	RW	32	0xffffffff	0000000000
CAM1_CAMDBCTL	0x7e801300	RW	32	0xffffffff	0000000000
CAM1_CAMIBSA1	0x7e801304	RW	32	0xffffffff	0000000000
CAM1_CAMIBEA1	0x7e801308	RW	32	0xffffffff	0000000000
CAM1_CAMIDI1	0x7e80130c	RW	32	0xffffffff	0000000000
CAM1_CAMDBSA1	0x7e801310	RW	32	0xffffffff	0000000000
CAM1_CAMDBEA1	0x7e801314	RW	32	0xffffffff	0000000000
CAM1_CAMMISC	0x7e801400	RW	32	0xffffffff	0000000000

CCP2TX

Info

base	0x7e001000
id	0x63637032

Registers

register name	address	type	width	mask	reset
CCP2TX_TC	0x7e001000	RW	32	0x8000ff07	0x0000ff00
CCP2TX_TS	0x7e001004	RW	20	0x000f1f7f	0000000000
CCP2TX_TAC	0x7e001008	RW	32	0xffffff0f	0x77434307
CCP2TX_TPC	0x7e00100c	RW	16	0x0000ffff	0000000000
CCP2TX_TSC	0x7e001010	RW	4	0x0000000f	0x00000002
CCP2TX_TIC	0x7e001014	RW	8	0x000000f7	0000000000
CCP2TX_TTC	0x7e001018	RW	32	0x80ff1fff	0x00000100
CCP2TX_TBA	0x7e00101c	RW	30	0x3fffffff	0000000000
CCP2TX_TDL	0x7e001020	RW	30	0x3fffffff	0000000000
CCP2TX_TD	0x7e001024	RW	8	0x000000ff
CCP2TX_TSPARE	0x7e001028	RW	32	0xffffffff

Register:CCP2TX_TC (0x7e001000)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TC_TEN	0	0	0x00000001	0xfffffffe	0x0
CCP2TX_TC_MEN	1	1	0x00000002	0xfffffffd	0x0
CCP2TX_TC_CLKM	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	7	NA	NA	NA
CCP2TX_TC_TIP	8	15	0x0000ff00	0xffff00ff	0xff
missing definiton	16	30	NA	NA	NA
CCP2TX_TC_SWR	31	31	0x80000000	0x7fffffff	0x0

Register:CCP2TX_TS (0x7e001004)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TS_TXB	0	0	0x00000001	0xfffffffe	0x0
CCP2TX_TS_IEB	1	1	0x00000002	0xfffffffd	0x0
CCP2TX_TS_ARE	2	2	0x00000004	0xfffffffb	0x0
CCP2TX_TS_TUE	3	3	0x00000008	0xfffffff7	0x0
CCP2TX_TS_TFE	4	4	0x00000010	0xffffffef	0x0
CCP2TX_TS_TFF	5	5	0x00000020	0xffffffdf	0x0
CCP2TX_TS_TFP	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
CCP2TX_TS_TQL	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	15	NA	NA	NA
CCP2TX_TS_IS	16	16	0x00010000	0xfffeffff	0x0
CCP2TX_TS_TII	17	17	0x00020000	0xfffdffff	0x0
CCP2TX_TS_TEI	18	18	0x00040000	0xfffbffff	0x0
CCP2TX_TS_TQI	19	19	0x00080000	0xfff7ffff	0x0

Register:CCP2TX_TAC (0x7e001008)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TAC_ARST	0	0	0x00000001	0xfffffffe	0x1
CCP2TX_TAC_APD	1	1	0x00000002	0xfffffffd	0x1
CCP2TX_TAC_BPD	2	2	0x00000004	0xfffffffb	0x1
CCP2TX_TAC_TPC	3	3	0x00000008	0xfffffff7	0x0
missing definiton	4	7	NA	NA	NA
CCP2TX_TAC_DLAC	8	15	0x0000ff00	0xffff00ff	0x43
CCP2TX_TAC_CLAC	16	23	0x00ff0000	0xff00ffff	0x43
CCP2TX_TAC_PTATADJ	24	27	0x0f000000	0xf0ffffff	0x7
CCP2TX_TAC_CTATADJ	28	31	0xf0000000	0x0fffffff	0x7

Register:CCP2TX_TPC (0x7e00100c)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TPC_TNP	0	3	0x0000000f	0xfffffff0	0x0
CCP2TX_TPC_TPP	4	7	0x000000f0	0xffffff0f	0x0
CCP2TX_TPC_TPT	8	15	0x0000ff00	0xffff00ff	0x0

Register:CCP2TX_TSC (0x7e001010)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TSC_TSM	0	3	0x0000000f	0xfffffff0	0x2

Register:CCP2TX_TIC (0x7e001014)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TIC_TIIE	0	0	0x00000001	0xfffffffe	0x0
CCP2TX_TIC_TEIE	1	1	0x00000002	0xfffffffd	0x0
CCP2TX_TIC_TQIE	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
CCP2TX_TIC_TQIT	4	7	0x000000f0	0xffffff0f	0x0

Register:CCP2TX_TTC (0x7e001018)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TTC_LCN	0	3	0x0000000f	0xfffffff0	0x0
CCP2TX_TTC_LSC	4	7	0x000000f0	0xffffff0f	0x0
CCP2TX_TTC_LEC	8	11	0x00000f00	0xfffff0ff	0x1
CCP2TX_TTC_FSP	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
CCP2TX_TTC_BI	16	23	0x00ff0000	0xff00ffff	0x0
missing definiton	24	30	NA	NA	NA
CCP2TX_TTC_ATX	31	31	0x80000000	0x7fffffff	0x0

Register:CCP2TX_TBA (0x7e00101c)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TBA_ADDR	0	29	0x3fffffff	0xc0000000	0x0

Register:CCP2TX_TDL (0x7e001020)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TDL_LEN	0	29	0x3fffffff	0xc0000000	0x0

Register:CCP2TX_TD (0x7e001024)

field_name	start_bit	end_bit	set	clear	reset
CCP2TX_TD_TCS	0	4	0x0000001f	0xffffffe0
CCP2TX_TD_IES	5	6	0x00000060	0xffffff9f

CM

Info

description	Clock manager
base	0x7e101000
id	0x0000636d
password	0x5a000000

Registers

register name	address	type	width	mask	reset
CM_GNRICCTL	0x7e101000	RW	20	0x000fffff	0000000000
CM_GNRICDIV	0x7e101004	RW	24	0x00ffffff	0000000000
CM_VPUCTL	0x7e101008	RW	10	0x000003cf	0x00000041
CM_VPUDIV	0x7e10100c	RW	24	0x00fffff0	0x00001000
CM_SYSCTL	0x7e101010	RW	7	0x00000040	0x00000040
CM_SYSDIV	0x7e101014	RO	13	0x00001000	0x00001000
CM_PERIACTL	0x7e101018	RW	7	0x00000040	0x00000040
CM_PERIADIV	0x7e10101c	RO	13	0x00001000	0x00001000
CM_PERIICTL	0x7e101020	RW	7	0x00000040	0000000000
CM_PERIIDIV	0x7e101024	RO	13	0x00001000	0x00001000
CM_H264CTL	0x7e101028	RW	10	0x000003ff	0x00000040
CM_H264DIV	0x7e10102c	RW	16	0x0000fff0	0000000000
CM_ISPCTL	0x7e101030	RW	10	0x000003ff	0x00000040
CM_ISPDIV	0x7e101034	RW	16	0x0000fff0	0000000000
CM_V3DCTL	0x7e101038	RW	10	0x000003ff	0x00000040
CM_V3DDIV	0x7e10103c	RW	16	0x0000fff0	0000000000
CM_CAM0CTL	0x7e101040	RW	10	0x000003bf	0000000000
CM_CAM0DIV	0x7e101044	RW	16	0x0000fff0	0000000000
CM_CAM1CTL	0x7e101048	RW	10	0x000003bf	0000000000
CM_CAM1DIV	0x7e10104c	RW	16	0x0000fff0	0000000000
CM_CCP2CTL	0x7e101050	RW	10	0x00000397	0000000000
CM_CCP2DIV	0x7e101054	RO	13	0x00001000	0x00001000
CM_DSI0ECTL	0x7e101058	RW	10	0x000003bf	0000000000
CM_DSI0EDIV	0x7e10105c	RW	16	0x0000fff0	0000000000
CM_DSI0PCTL	0x7e101060	RW	10	0x0000039f	0000000000
CM_DSI0PDIV	0x7e101064	RO	13	0x00001000	0x00001000
CM_DPICTL	0x7e101068	RW	10	0x000003bf	0000000000
CM_DPIDIV	0x7e10106c	RW	16	0x0000fff0	0000000000
CM_GP0CTL	0x7e101070	RW	11	0x000007bf	0x00000200
CM_GP0DIV	0x7e101074	RW	24	0x00ffffff	0000000000
CM_GP1CTL	0x7e101078	RW	11	0x000007bf	0x00000200
CM_GP1DIV	0x7e10107c	RW	24	0x00ffffff	0000000000
CM_GP2CTL	0x7e101080	RW	10	0x000003bf	0000000000
CM_GP2DIV	0x7e101084	RW	24	0x00ffffff	0000000000
CM_HSMCTL	0x7e101088	RW	10	0x000003ff	0000000000
CM_HSMDIV	0x7e10108c	RW	16	0x0000fff0	0000000000
CM_OTPCTL	0x7e101090	RW	10	0x000003b3	0x00000011
CM_OTPDIV	0x7e101094	RW	17	0x0001f000	0x00004000
CM_PCMCTL	0x7e101098	RW	11	0x000007bf	0x00000200
CM_PCMDIV	0x7e10109c	RW	24	0x00ffffff	0000000000
CM_PWMCTL	0x7e1010a0	RW	11	0x000007bf	0x00000200
CM_PWMDIV	0x7e1010a4	RW	24	0x00ffffff	0000000000
CM_SLIMCTL	0x7e1010a8	RW	11	0x000007bf	0x00000200
CM_SLIMDIV	0x7e1010ac	RW	24	0x00ffffff	0000000000
CM_SMICTL	0x7e1010b0	RW	10	0x000003bf	0000000000
CM_SMIDIV	0x7e1010b4	RW	16	0x0000fff0	0000000000
CM_TCNTCTL	0x7e1010c0	RW	14	0x000030cf	0000000000
CM_TCNTCNT	0x7e1010c4	RW	24	0x00ffffff	0000000000
CM_TECCTL	0x7e1010c8	RW	10	0x000003b3	0000000000
CM_TECDIV	0x7e1010cc	RW	18	0x0003f000	0000000000
CM_TD0CTL	0x7e1010d0	RW	13	0x00001bff	0000000000
CM_TD0DIV	0x7e1010d4	RW	24	0x00ffffff	0000000000
CM_TD1CTL	0x7e1010d8	RW	13	0x00001bff	0000000000
CM_TD1DIV	0x7e1010dc	RW	24	0x00ffffff	0000000000
CM_TSENSCTL	0x7e1010e0	RW	10	0x000003b3	0000000000
CM_TSENSDIV	0x7e1010e4	RW	17	0x0001f000	0000000000
CM_TIMERCTL	0x7e1010e8	RW	10	0x000003b3	0000000000
CM_TIMERDIV	0x7e1010ec	RW	18	0x0003ffff	0000000000
CM_UARTCTL	0x7e1010f0	RW	10	0x000003bf	0000000000
CM_UARTDIV	0x7e1010f4	RW	22	0x003fffff	0000000000
CM_VECCTL	0x7e1010f8	RW	10	0x000003bf	0000000000
CM_VECDIV	0x7e1010fc	RW	16	0x0000f000	0000000000
CM_OSCCOUNT	0x7e101100	RW	24	0x00ffffff	0000000000
CM_PLLA	0x7e101104	RW	10	0x000003ff	0x00000300
CM_PLLC	0x7e101108	RW	10	0x000003ff	0x00000300
CM_PLLD	0x7e10110c	RW	10	0x000003ff	0x00000300
CM_PLLH	0x7e101110	RW	10	0x00000307	0x00000300
CM_LOCK	0x7e101114	RW	13	0x00001f1f	0000000000
CM_EVENT	0x7e101118	RW	24	0x00ffffff	0000000000
CM_INTEN	0x7e10111c	RW	24	0x00ffffff	0000000000
CM_DSI0HSCK	0x7e101120	RW	1	0x00000001	0000000000
CM_CKSM	0x7e101124	RW	22	0x003fffff	0000000000
CM_OSCFREQI	0x7e101128	RW	8	0x000000ff	0000000000
CM_OSCFREQF	0x7e10112c	RW	20	0x000fffff	0000000000
CM_PLLTCTL	0x7e101130	RW	8	0x000000a7	0000000000
CM_PLLTCNT0	0x7e101134	RW	24	0x00ffffff	0000000000
CM_PLLTCNT1	0x7e101138	RW	24	0x00ffffff	0000000000
CM_PLLTCNT2	0x7e10113c	RW	24	0x00ffffff	0000000000
CM_PLLTCNT3	0x7e101140	RW	24	0x00ffffff	0000000000
CM_TDCLKEN	0x7e101144	RW	14	0x00003fff	0000000000
CM_BURSTCTL	0x7e101148	RW	8	0x000000b0	0000000000
CM_BURSTCNT	0x7e10114c	RW	24	0x00ffffff	0000000000
CM_DSI1ECTL	0x7e101158	RW	10	0x000003bf	0000000000
CM_DSI1EDIV	0x7e10115c	RW	16	0x0000fff0	0000000000
CM_DSI1PCTL	0x7e101160	RW	10	0x0000039f	0000000000
CM_DSI1PDIV	0x7e101164	RO	13	0x00001000	0x00001000
CM_DFTCTL	0x7e101168	RW	10	0x000003bf	0000000000
CM_DFTDIV	0x7e10116c	RW	17	0x0001f000	0000000000
CM_PLLB	0x7e101170	RW	10	0x00000303	0x00000300
CM_PULSECTL	0x7e101190	RW	10	0x000003b3	0x00000011
CM_PULSEDIV	0x7e101194	RW	24	0x00fff000	0x0001b000
CM_SDCCTL	0x7e1011a8	RW	18	0x0003f3bf	0x00004000
CM_SDCDIV	0x7e1011ac	RW	18	0x0003f000	0000000000
CM_ARMCTL	0x7e1011b0	RW	13	0x000013bf	0x00000004
CM_ARMDIV	0x7e1011b4	RO	13	0x00001000	0x00001000
CM_AVEOCTL	0x7e1011b8	RW	10	0x000003bf	0000000000
CM_AVEODIV	0x7e1011bc	RW	16	0x0000f000	0000000000
CM_EMMCCTL	0x7e1011c0	RW	10	0x000003bf	0000000000
CM_EMMCDIV	0x7e1011c4	RW	16	0x0000fff0	0000000000

Register:CM_GNRICCTL (0x7e101000)

field_name	start_bit	end_bit	set	clear	reset
CM_GNRICCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_GNRICCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_GNRICCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_GNRICCTL_GATE	6	6	0x00000040	0xffffffbf	0x0
CM_GNRICCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_GNRICCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_GNRICCTL_MASH	9	10	0x00000600	0xfffff9ff	0x0
CM_GNRICCTL_FLIP	11	11	0x00000800	0xfffff7ff	0x0

Register:CM_GNRICDIV (0x7e101004)

field_name	start_bit	end_bit	set	clear	reset
CM_GNRICDIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_VPUCTL (0x7e101008)

field_name	start_bit	end_bit	set	clear	reset
CM_VPUCTL_SRC	0	3	0x0000000f	0xfffffff0	0x1
missing definiton	4	5	NA	NA	NA
CM_VPUCTL_GATE	6	6	0x00000040	0xffffffbf	0x1
CM_VPUCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_VPUCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_VPUCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_VPUDIV (0x7e10100c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_VPUDIV_DIV	4	23	0x00fffff0	0xff00000f	0x100

Register:CM_SYSCTL (0x7e101010)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	5	NA	NA	NA
CM_SYSCTL_GATE	6	6	0x00000040	0xffffffbf	0x1

Register:CM_SYSDIV (0x7e101014)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_SYSDIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_PERIACTL (0x7e101018)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	5	NA	NA	NA
CM_PERIACTL_GATE	6	6	0x00000040	0xffffffbf	0x1

Register:CM_PERIADIV (0x7e10101c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_PERIADIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_PERIICTL (0x7e101020)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	5	NA	NA	NA
CM_PERIICTL_GATE	6	6	0x00000040	0xffffffbf	0x0

Register:CM_PERIIDIV (0x7e101024)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_PERIIDIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_H264CTL (0x7e101028)

field_name	start_bit	end_bit	set	clear	reset
CM_H264CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_H264CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_H264CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_H264CTL_GATE	6	6	0x00000040	0xffffffbf	0x1
CM_H264CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_H264CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_H264CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_H264DIV (0x7e10102c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_H264DIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_ISPCTL (0x7e101030)

field_name	start_bit	end_bit	set	clear	reset
CM_ISPCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_ISPCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_ISPCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_ISPCTL_GATE	6	6	0x00000040	0xffffffbf	0x1
CM_ISPCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_ISPCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_ISPCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_ISPDIV (0x7e101034)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_ISPDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_V3DCTL (0x7e101038)

field_name	start_bit	end_bit	set	clear	reset
CM_V3DCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_V3DCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_V3DCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_V3DCTL_GATE	6	6	0x00000040	0xffffffbf	0x1
CM_V3DCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_V3DCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_V3DCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_V3DDIV (0x7e10103c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_V3DDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_CAM0CTL (0x7e101040)

field_name	start_bit	end_bit	set	clear	reset
CM_CAM0CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_CAM0CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_CAM0CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_CAM0CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_CAM0CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_CAM0CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_CAM0DIV (0x7e101044)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_CAM0DIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_CAM1CTL (0x7e101048)

field_name	start_bit	end_bit	set	clear	reset
CM_CAM1CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_CAM1CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_CAM1CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_CAM1CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_CAM1CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_CAM1CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_CAM1DIV (0x7e10104c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_CAM1DIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_CCP2CTL (0x7e101050)

field_name	start_bit	end_bit	set	clear	reset
CM_CCP2CTL_SRC	0	2	0x00000007	0xfffffff8	0x0
missing definiton	3	3	NA	NA	NA
CM_CCP2CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	6	NA	NA	NA
CM_CCP2CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_CCP2CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_CCP2CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_CCP2DIV (0x7e101054)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_CCP2DIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_DSI0ECTL (0x7e101058)

field_name	start_bit	end_bit	set	clear	reset
CM_DSI0ECTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DSI0ECTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_DSI0ECTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_DSI0ECTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DSI0ECTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DSI0ECTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DSI0EDIV (0x7e10105c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_DSI0EDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_DSI0PCTL (0x7e101060)

field_name	start_bit	end_bit	set	clear	reset
CM_DSI0PCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DSI0PCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	6	NA	NA	NA
CM_DSI0PCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DSI0PCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DSI0PCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DSI0PDIV (0x7e101064)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_DSI0PDIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_DPICTL (0x7e101068)

field_name	start_bit	end_bit	set	clear	reset
CM_DPICTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DPICTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_DPICTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_DPICTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DPICTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DPICTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DPIDIV (0x7e10106c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_DPIDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_GP0CTL (0x7e101070)

field_name	start_bit	end_bit	set	clear	reset
CM_GP0CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_GP0CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_GP0CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_GP0CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_GP0CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_GP0CTL_MASH	9	10	0x00000600	0xfffff9ff	0x1

Register:CM_GP0DIV (0x7e101074)

field_name	start_bit	end_bit	set	clear	reset
CM_GP0DIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_GP1CTL (0x7e101078)

field_name	start_bit	end_bit	set	clear	reset
CM_GP1CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_GP1CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_GP1CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_GP1CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_GP1CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_GP1CTL_MASH	9	10	0x00000600	0xfffff9ff	0x1

Register:CM_GP1DIV (0x7e10107c)

field_name	start_bit	end_bit	set	clear	reset
CM_GP1DIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_GP2CTL (0x7e101080)

field_name	start_bit	end_bit	set	clear	reset
CM_GP2CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_GP2CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_GP2CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_GP2CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_GP2CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_GP2CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_GP2DIV (0x7e101084)

field_name	start_bit	end_bit	set	clear	reset
CM_GP2DIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_HSMCTL (0x7e101088)

field_name	start_bit	end_bit	set	clear	reset
CM_HSMCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_HSMCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_HSMCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_HSMCTL_GATE	6	6	0x00000040	0xffffffbf	0x0
CM_HSMCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_HSMCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_HSMCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_HSMDIV (0x7e10108c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_HSMDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_OTPCTL (0x7e101090)

field_name	start_bit	end_bit	set	clear	reset
CM_OTPCTL_SRC	0	1	0x00000003	0xfffffffc	0x1
missing definiton	2	3	NA	NA	NA
CM_OTPCTL_ENAB	4	4	0x00000010	0xffffffef	0x1
CM_OTPCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_OTPCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_OTPCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_OTPCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_OTPDIV (0x7e101094)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_OTPDIV_DIV	12	16	0x0001f000	0xfffe0fff	0x4

Register:CM_PCMCTL (0x7e101098)

field_name	start_bit	end_bit	set	clear	reset
CM_PCMCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_PCMCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_PCMCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_PCMCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_PCMCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_PCMCTL_MASH	9	10	0x00000600	0xfffff9ff	0x1

Register:CM_PCMDIV (0x7e10109c)

field_name	start_bit	end_bit	set	clear	reset
CM_PCMDIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_PWMCTL (0x7e1010a0)

field_name	start_bit	end_bit	set	clear	reset
CM_PWMCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_PWMCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_PWMCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_PWMCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_PWMCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_PWMCTL_MASH	9	10	0x00000600	0xfffff9ff	0x1

Register:CM_PWMDIV (0x7e1010a4)

field_name	start_bit	end_bit	set	clear	reset
CM_PWMDIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_SLIMCTL (0x7e1010a8)

field_name	start_bit	end_bit	set	clear	reset
CM_SLIMCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_SLIMCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_SLIMCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_SLIMCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_SLIMCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_SLIMCTL_MASH	9	10	0x00000600	0xfffff9ff	0x1

Register:CM_SLIMDIV (0x7e1010ac)

field_name	start_bit	end_bit	set	clear	reset
CM_SLIMDIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_SMICTL (0x7e1010b0)

field_name	start_bit	end_bit	set	clear	reset
CM_SMICTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_SMICTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_SMICTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_SMICTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_SMICTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_SMICTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_SMIDIV (0x7e1010b4)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_SMIDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_TCNTCTL (0x7e1010c0)

field_name	start_bit	end_bit	set	clear	reset
CM_TCNTCTL_SRC0	0	3	0x0000000f	0xfffffff0	0x0
missing definiton	4	5	NA	NA	NA
CM_TCNTCTL_KILL	6	6	0x00000040	0xffffffbf	0x0
CM_TCNTCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
missing definiton	8	11	NA	NA	NA
CM_TCNTCTL_SRC1	12	13	0x00003000	0xffffcfff	0x0

Register:CM_TCNTCNT (0x7e1010c4)

field_name	start_bit	end_bit	set	clear	reset
CM_TCNTCNT_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_TECCTL (0x7e1010c8)

field_name	start_bit	end_bit	set	clear	reset
CM_TECCTL_SRC	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	3	NA	NA	NA
CM_TECCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_TECCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_TECCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_TECCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_TECCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_TECDIV (0x7e1010cc)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_TECDIV_DIV	12	17	0x0003f000	0xfffc0fff	0x0

Register:CM_TD0CTL (0x7e1010d0)

field_name	start_bit	end_bit	set	clear	reset
CM_TD0CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_TD0CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_TD0CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_TD0CTL_GATE	6	6	0x00000040	0xffffffbf	0x0
CM_TD0CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_TD0CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_TD0CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	10	NA	NA	NA
CM_TD0CTL_FLIP	11	11	0x00000800	0xfffff7ff	0x0
CM_TD0CTL_STEP	12	12	0x00001000	0xffffefff	0x0

Register:CM_TD0DIV (0x7e1010d4)

field_name	start_bit	end_bit	set	clear	reset
CM_TD0DIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_TD1CTL (0x7e1010d8)

field_name	start_bit	end_bit	set	clear	reset
CM_TD1CTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_TD1CTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_TD1CTL_KILL	5	5	0x00000020	0xffffffdf	0x0
CM_TD1CTL_GATE	6	6	0x00000040	0xffffffbf	0x0
CM_TD1CTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_TD1CTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_TD1CTL_FRAC	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	10	NA	NA	NA
CM_TD1CTL_FLIP	11	11	0x00000800	0xfffff7ff	0x0
CM_TD1CTL_STEP	12	12	0x00001000	0xffffefff	0x0

Register:CM_TD1DIV (0x7e1010dc)

field_name	start_bit	end_bit	set	clear	reset
CM_TD1DIV_DIV	0	23	0x00ffffff	0xff000000	0x0

Register:CM_TSENSCTL (0x7e1010e0)

field_name	start_bit	end_bit	set	clear	reset
CM_TSENSCTL_SRC	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	3	NA	NA	NA
CM_TSENSCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_TSENSCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_TSENSCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_TSENSCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_TSENSCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_TSENSDIV (0x7e1010e4)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_TSENSDIV_DIV	12	16	0x0001f000	0xfffe0fff	0x0

Register:CM_TIMERCTL (0x7e1010e8)

field_name	start_bit	end_bit	set	clear	reset
CM_TIMERCTL_SRC	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	3	NA	NA	NA
CM_TIMERCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_TIMERCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_TIMERCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_TIMERCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_TIMERCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_TIMERDIV (0x7e1010ec)

field_name	start_bit	end_bit	set	clear	reset
CM_TIMERDIV_DIV	0	17	0x0003ffff	0xfffc0000	0x0

Register:CM_UARTCTL (0x7e1010f0)

field_name	start_bit	end_bit	set	clear	reset
CM_UARTCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_UARTCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_UARTCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_UARTCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_UARTCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_UARTCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_UARTDIV (0x7e1010f4)

field_name	start_bit	end_bit	set	clear	reset
CM_UARTDIV_DIV	0	21	0x003fffff	0xffc00000	0x0

Register:CM_VECCTL (0x7e1010f8)

field_name	start_bit	end_bit	set	clear	reset
CM_VECCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_VECCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_VECCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_VECCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_VECCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_VECCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_VECDIV (0x7e1010fc)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_VECDIV_DIV	12	15	0x0000f000	0xffff0fff	0x0

Register:CM_OSCCOUNT (0x7e101100)

field_name	start_bit	end_bit	set	clear	reset
CM_OSCCOUNT_NUM	0	23	0x00ffffff	0xff000000	0x0

Register:CM_PLLA (0x7e101104)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLA_LOADDSI0	0	0	0x00000001	0xfffffffe	0x0
CM_PLLA_HOLDDSI0	1	1	0x00000002	0xfffffffd	0x0
CM_PLLA_LOADCCP2	2	2	0x00000004	0xfffffffb	0x0
CM_PLLA_HOLDCCP2	3	3	0x00000008	0xfffffff7	0x0
CM_PLLA_LOADCORE	4	4	0x00000010	0xffffffef	0x0
CM_PLLA_HOLDCORE	5	5	0x00000020	0xffffffdf	0x0
CM_PLLA_LOADPER	6	6	0x00000040	0xffffffbf	0x0
CM_PLLA_HOLDPER	7	7	0x00000080	0xffffff7f	0x0
CM_PLLA_ANARST	8	8	0x00000100	0xfffffeff	0x1
CM_PLLA_DIGRST	9	9	0x00000200	0xfffffdff	0x1

Register:CM_PLLC (0x7e101108)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLC_LOADCORE0	0	0	0x00000001	0xfffffffe	0x0
CM_PLLC_HOLDCORE0	1	1	0x00000002	0xfffffffd	0x0
CM_PLLC_LOADCORE1	2	2	0x00000004	0xfffffffb	0x0
CM_PLLC_HOLDCORE1	3	3	0x00000008	0xfffffff7	0x0
CM_PLLC_LOADCORE2	4	4	0x00000010	0xffffffef	0x0
CM_PLLC_HOLDCORE2	5	5	0x00000020	0xffffffdf	0x0
CM_PLLC_LOADPER	6	6	0x00000040	0xffffffbf	0x0
CM_PLLC_HOLDPER	7	7	0x00000080	0xffffff7f	0x0
CM_PLLC_ANARST	8	8	0x00000100	0xfffffeff	0x1
CM_PLLC_DIGRST	9	9	0x00000200	0xfffffdff	0x1

Register:CM_PLLD (0x7e10110c)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLD_LOADDSI0	0	0	0x00000001	0xfffffffe	0x0
CM_PLLD_HOLDDSI0	1	1	0x00000002	0xfffffffd	0x0
CM_PLLD_LOADDSI1	2	2	0x00000004	0xfffffffb	0x0
CM_PLLD_HOLDDSI1	3	3	0x00000008	0xfffffff7	0x0
CM_PLLD_LOADCORE	4	4	0x00000010	0xffffffef	0x0
CM_PLLD_HOLDCORE	5	5	0x00000020	0xffffffdf	0x0
CM_PLLD_LOADPER	6	6	0x00000040	0xffffffbf	0x0
CM_PLLD_HOLDPER	7	7	0x00000080	0xffffff7f	0x0
CM_PLLD_ANARST	8	8	0x00000100	0xfffffeff	0x1
CM_PLLD_DIGRST	9	9	0x00000200	0xfffffdff	0x1

Register:CM_PLLH (0x7e101110)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLH_LOADPIX	0	0	0x00000001	0xfffffffe	0x0
CM_PLLH_LOADAUX	1	1	0x00000002	0xfffffffd	0x0
CM_PLLH_LOADRCAL	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	7	NA	NA	NA
CM_PLLH_ANARST	8	8	0x00000100	0xfffffeff	0x1
CM_PLLH_DIGRST	9	9	0x00000200	0xfffffdff	0x1

Register:CM_LOCK (0x7e101114)

field_name	start_bit	end_bit	set	clear	reset
CM_LOCK_LOCKA	0	0	0x00000001	0xfffffffe	0x0
CM_LOCK_LOCKB	1	1	0x00000002	0xfffffffd	0x0
CM_LOCK_LOCKC	2	2	0x00000004	0xfffffffb	0x0
CM_LOCK_LOCKD	3	3	0x00000008	0xfffffff7	0x0
CM_LOCK_LOCKH	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	7	NA	NA	NA
CM_LOCK_FLOCKA	8	8	0x00000100	0xfffffeff	0x0
CM_LOCK_FLOCKB	9	9	0x00000200	0xfffffdff	0x0
CM_LOCK_FLOCKC	10	10	0x00000400	0xfffffbff	0x0
CM_LOCK_FLOCKD	11	11	0x00000800	0xfffff7ff	0x0
CM_LOCK_FLOCKH	12	12	0x00001000	0xffffefff	0x0

Register:CM_EVENT (0x7e101118)

field_name	start_bit	end_bit	set	clear	reset
CM_EVENT_GAINA	0	0	0x00000001	0xfffffffe	0x0
CM_EVENT_GAINB	1	1	0x00000002	0xfffffffd	0x0
CM_EVENT_GAINC	2	2	0x00000004	0xfffffffb	0x0
CM_EVENT_GAIND	3	3	0x00000008	0xfffffff7	0x0
CM_EVENT_GAINH	4	4	0x00000010	0xffffffef	0x0
CM_EVENT_LOSSA	5	5	0x00000020	0xffffffdf	0x0
CM_EVENT_LOSSB	6	6	0x00000040	0xffffffbf	0x0
CM_EVENT_LOSSC	7	7	0x00000080	0xffffff7f	0x0
CM_EVENT_LOSSD	8	8	0x00000100	0xfffffeff	0x0
CM_EVENT_LOSSH	9	9	0x00000200	0xfffffdff	0x0
CM_EVENT_FGAINA	10	10	0x00000400	0xfffffbff	0x0
CM_EVENT_FGAINB	11	11	0x00000800	0xfffff7ff	0x0
CM_EVENT_FGAINC	12	12	0x00001000	0xffffefff	0x0
CM_EVENT_FGAIND	13	13	0x00002000	0xffffdfff	0x0
CM_EVENT_FLOSSA	14	14	0x00004000	0xffffbfff	0x0
CM_EVENT_FLOSSB	15	15	0x00008000	0xffff7fff	0x0
CM_EVENT_FLOSSC	16	16	0x00010000	0xfffeffff	0x0
CM_EVENT_FLOSSD	17	17	0x00020000	0xfffdffff	0x0
CM_EVENT_BADPASS	18	18	0x00040000	0xfffbffff	0x0
CM_EVENT_WRFAIL	19	19	0x00080000	0xfff7ffff	0x0
CM_EVENT_A2WDONE	20	20	0x00100000	0xffefffff	0x0
CM_EVENT_OCDONE	21	21	0x00200000	0xffdfffff	0x0
CM_EVENT_RESUS	22	22	0x00400000	0xffbfffff	0x0
CM_EVENT_BURSTDONE	23	23	0x00800000	0xff7fffff	0x0

Register:CM_INTEN (0x7e10111c)

field_name	start_bit	end_bit	set	clear	reset
CM_INTEN_GAINA	0	0	0x00000001	0xfffffffe	0x0
CM_INTEN_GAINB	1	1	0x00000002	0xfffffffd	0x0
CM_INTEN_GAINC	2	2	0x00000004	0xfffffffb	0x0
CM_INTEN_GAIND	3	3	0x00000008	0xfffffff7	0x0
CM_INTEN_GAINH	4	4	0x00000010	0xffffffef	0x0
CM_INTEN_LOSSA	5	5	0x00000020	0xffffffdf	0x0
CM_INTEN_LOSSB	6	6	0x00000040	0xffffffbf	0x0
CM_INTEN_LOSSC	7	7	0x00000080	0xffffff7f	0x0
CM_INTEN_LOSSD	8	8	0x00000100	0xfffffeff	0x0
CM_INTEN_LOSSH	9	9	0x00000200	0xfffffdff	0x0
CM_INTEN_FGAINA	10	10	0x00000400	0xfffffbff	0x0
CM_INTEN_FGAINB	11	11	0x00000800	0xfffff7ff	0x0
CM_INTEN_FGAINC	12	12	0x00001000	0xffffefff	0x0
CM_INTEN_FGAIND	13	13	0x00002000	0xffffdfff	0x0
CM_INTEN_FLOSSA	14	14	0x00004000	0xffffbfff	0x0
CM_INTEN_FLOSSB	15	15	0x00008000	0xffff7fff	0x0
CM_INTEN_FLOSSC	16	16	0x00010000	0xfffeffff	0x0
CM_INTEN_FLOSSD	17	17	0x00020000	0xfffdffff	0x0
CM_INTEN_BADPASS	18	18	0x00040000	0xfffbffff	0x0
CM_INTEN_WRFAIL	19	19	0x00080000	0xfff7ffff	0x0
CM_INTEN_A2WDONE	20	20	0x00100000	0xffefffff	0x0
CM_INTEN_OCDONE	21	21	0x00200000	0xffdfffff	0x0
CM_INTEN_RESUS	22	22	0x00400000	0xffbfffff	0x0
CM_INTEN_BURSTDONE	23	23	0x00800000	0xff7fffff	0x0

Register:CM_DSI0HSCK (0x7e101120)

field_name	start_bit	end_bit	set	clear	reset
CM_DSI0HSCK_SELPLLD	0	0	0x00000001	0xfffffffe	0x0

Register:CM_CKSM (0x7e101124)

field_name	start_bit	end_bit	set	clear	reset
CM_CKSM_STATE	0	7	0x000000ff	0xffffff00	0x0
CM_CKSM_FRCE	8	15	0x0000ff00	0xffff00ff	0x0
CM_CKSM_CFG	16	17	0x00030000	0xfffcffff	0x0
CM_CKSM_OSC	18	19	0x000c0000	0xfff3ffff	0x0
CM_CKSM_AUTO	20	20	0x00100000	0xffefffff	0x0
CM_CKSM_STEP	21	21	0x00200000	0xffdfffff	0x0

Register:CM_OSCFREQI (0x7e101128)

field_name	start_bit	end_bit	set	clear	reset
CM_OSCFREQI_INT	0	7	0x000000ff	0xffffff00	0x0

Register:CM_OSCFREQF (0x7e10112c)

field_name	start_bit	end_bit	set	clear	reset
CM_OSCFREQF_FRAC	0	19	0x000fffff	0xfff00000	0x0

Register:CM_PLLTCTL (0x7e101130)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLTCTL_SRC	0	2	0x00000007	0xfffffff8	0x0
missing definiton	3	4	NA	NA	NA
CM_PLLTCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_PLLTCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0

Register:CM_PLLTCNT0 (0x7e101134)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLTCNT0_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_PLLTCNT1 (0x7e101138)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLTCNT1_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_PLLTCNT2 (0x7e10113c)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLTCNT2_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_PLLTCNT3 (0x7e101140)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLTCNT3_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_TDCLKEN (0x7e101144)

field_name	start_bit	end_bit	set	clear	reset
CM_TDCLKEN_PLLABYP	0	0	0x00000001	0xfffffffe	0x0
CM_TDCLKEN_PLLBBYP	1	1	0x00000002	0xfffffffd	0x0
CM_TDCLKEN_PLLCBYP	2	2	0x00000004	0xfffffffb	0x0
CM_TDCLKEN_PLLDBYP	3	3	0x00000008	0xfffffff7	0x0
CM_TDCLKEN_PLLADIV2	4	4	0x00000010	0xffffffef	0x0
CM_TDCLKEN_PLLBDIV2	5	5	0x00000020	0xffffffdf	0x0
CM_TDCLKEN_PLLCDIV2	6	6	0x00000040	0xffffffbf	0x0
CM_TDCLKEN_PLLDDIV2	7	7	0x00000080	0xffffff7f	0x0
CM_TDCLKEN_HDMIBYP	8	8	0x00000100	0xfffffeff	0x0
CM_TDCLKEN_MPHIWDFT	9	9	0x00000200	0xfffffdff	0x0
CM_TDCLKEN_MPHIRDFT	10	10	0x00000400	0xfffffbff	0x0
CM_TDCLKEN_USBDFT	11	11	0x00000800	0xfffff7ff	0x0
CM_TDCLKEN_SLIMDFT	12	12	0x00001000	0xffffefff	0x0
CM_TDCLKEN_IMAGETD	13	13	0x00002000	0xffffdfff	0x0

Register:CM_BURSTCTL (0x7e101148)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_BURSTCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_BURSTCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_BURSTCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0

Register:CM_BURSTCNT (0x7e10114c)

field_name	start_bit	end_bit	set	clear	reset
CM_BURSTCNT_CNT	0	23	0x00ffffff	0xff000000	0x0

Register:CM_DSI1ECTL (0x7e101158)

field_name	start_bit	end_bit	set	clear	reset
CM_DSI1ECTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DSI1ECTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_DSI1ECTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_DSI1ECTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DSI1ECTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DSI1ECTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DSI1EDIV (0x7e10115c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_DSI1EDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

Register:CM_DSI1PCTL (0x7e101160)

field_name	start_bit	end_bit	set	clear	reset
CM_DSI1PCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DSI1PCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	6	NA	NA	NA
CM_DSI1PCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DSI1PCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DSI1PCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DSI1PDIV (0x7e101164)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_DSI1PDIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_DFTCTL (0x7e101168)

field_name	start_bit	end_bit	set	clear	reset
CM_DFTCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_DFTCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_DFTCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_DFTCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_DFTCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_DFTCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_DFTDIV (0x7e10116c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_DFTDIV_DIV	12	16	0x0001f000	0xfffe0fff	0x0

Register:CM_PLLB (0x7e101170)

field_name	start_bit	end_bit	set	clear	reset
CM_PLLB_LOADARM	0	0	0x00000001	0xfffffffe	0x0
CM_PLLB_HOLDARM	1	1	0x00000002	0xfffffffd	0x0
missing definiton	2	7	NA	NA	NA
CM_PLLB_ANARST	8	8	0x00000100	0xfffffeff	0x1
CM_PLLB_DIGRST	9	9	0x00000200	0xfffffdff	0x1

Register:CM_PULSECTL (0x7e101190)

field_name	start_bit	end_bit	set	clear	reset
CM_PULSECTL_SRC	0	1	0x00000003	0xfffffffc	0x1
missing definiton	2	3	NA	NA	NA
CM_PULSECTL_ENAB	4	4	0x00000010	0xffffffef	0x1
CM_PULSECTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_PULSECTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_PULSECTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_PULSECTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_PULSEDIV (0x7e101194)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_PULSEDIV_DIV	12	23	0x00fff000	0xff000fff	0x1b

Register:CM_SDCCTL (0x7e1011a8)

field_name	start_bit	end_bit	set	clear	reset
CM_SDCCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_SDCCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_SDCCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_SDCCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_SDCCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_SDCCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	11	NA	NA	NA
CM_SDCCTL_CTRL	12	15	0x0000f000	0xffff0fff	0x4
CM_SDCCTL_ACCPT	16	16	0x00010000	0xfffeffff	0x0
CM_SDCCTL_UPDATE	17	17	0x00020000	0xfffdffff	0x0

Register:CM_SDCDIV (0x7e1011ac)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_SDCDIV_DIV	12	17	0x0003f000	0xfffc0fff	0x0

Register:CM_ARMCTL (0x7e1011b0)

field_name	start_bit	end_bit	set	clear	reset
CM_ARMCTL_SRC	0	3	0x0000000f	0xfffffff0	0x4
CM_ARMCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_ARMCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_ARMCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_ARMCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_ARMCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	11	NA	NA	NA
CM_ARMCTL_AXIHALF	12	12	0x00001000	0xffffefff	0x0

Register:CM_ARMDIV (0x7e1011b4)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_ARMDIV_DIV	12	12	0x00001000	0xffffefff	0x1

Register:CM_AVEOCTL (0x7e1011b8)

field_name	start_bit	end_bit	set	clear	reset
CM_AVEOCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_AVEOCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_AVEOCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_AVEOCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_AVEOCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_AVEOCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_AVEODIV (0x7e1011bc)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	11	NA	NA	NA
CM_AVEODIV_DIV	12	15	0x0000f000	0xffff0fff	0x0

Register:CM_EMMCCTL (0x7e1011c0)

field_name	start_bit	end_bit	set	clear	reset
CM_EMMCCTL_SRC	0	3	0x0000000f	0xfffffff0	0x0
CM_EMMCCTL_ENAB	4	4	0x00000010	0xffffffef	0x0
CM_EMMCCTL_KILL	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
CM_EMMCCTL_BUSY	7	7	0x00000080	0xffffff7f	0x0
CM_EMMCCTL_BUSYD	8	8	0x00000100	0xfffffeff	0x0
CM_EMMCCTL_FRAC	9	9	0x00000200	0xfffffdff	0x0

Register:CM_EMMCDIV (0x7e1011c4)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	3	NA	NA	NA
CM_EMMCDIV_DIV	4	15	0x0000fff0	0xffff000f	0x0

CMI

Info

base	0x7e802000
id	0x00636d69
password	0x5a000000

Registers

register name	address	type	width	mask	reset
CMI_CAM0	0x7e802000	RW	6	0x0000003f	0000000000
CMI_CAM1	0x7e802004	RW	10	0x000003ff	0000000000
CMI_CAMTEST	0x7e802008	RW	5	0x0000001f	0000000000
CMI_USBCTL	0x7e802010	RW	7	0x00000040	0x00000040

Register:CMI_CAM0 (0x7e802000)

field_name	start_bit	end_bit	set	clear	reset
CMI_CAM0_HSSRC	0	1	0x00000003	0xfffffffc	0x0
CMI_CAM0_RX0SRC	2	3	0x0000000c	0xfffffff3	0x0
CMI_CAM0_RX1SRC	4	5	0x00000030	0xffffffcf	0x0

Register:CMI_CAM1 (0x7e802004)

field_name	start_bit	end_bit	set	clear	reset
CMI_CAM1_HSSRC	0	1	0x00000003	0xfffffffc	0x0
CMI_CAM1_RX0SRC	2	3	0x0000000c	0xfffffff3	0x0
CMI_CAM1_RX1SRC	4	5	0x00000030	0xffffffcf	0x0
CMI_CAM1_RX2SRC	6	7	0x000000c0	0xffffff3f	0x0
CMI_CAM1_RX3SRC	8	9	0x00000300	0xfffffcff	0x0

Register:CMI_CAMTEST (0x7e802008)

field_name	start_bit	end_bit	set	clear	reset
CMI_CAMTEST_SRC	0	3	0x0000000f	0xfffffff0	0x0
CMI_CAMTEST_ENAB	4	4	0x00000010	0xffffffef	0x0

Register:CMI_USBCTL (0x7e802010)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	5	NA	NA	NA
CMI_USBCTL_GATE	6	6	0x00000040	0xffffffbf	0x1

CPG

Info

base	0x7e211000
id	0x67706320

Registers

register name	address	type	width	mask
CPG_Config	0x7e211000	RW	32	0xffffffff
CPG_IntStatus	0x7e211004	RW	32	0xffffffff
CPG_Trigger	0x7e211008	RW	2	0x00000003
CPG_Param0	0x7e211010	RW	32	0xffffffff
CPG_Param1	0x7e211014	RW	32	0xffffffff
CPG_Param2	0x7e211018	RW	32	0xffffffff
CPG_Param3	0x7e21101c	RW	32	0xffffffff
CPG_Debug0	0x7e211040	RW	32	0xffffffff
CPG_Debug1	0x7e211044	RW	32	0xffffffff
CPG_Debug2	0x7e211048	RW	32	0xffffffff
CPG_Debug3	0x7e21104c	RW	32	0xffffffff

DMA

Info

base	0x7e007fe0

Registers

register name	address	type	width	mask	reset
DMA_INT_STATUS	0x7e007fe0	RO	16	0x0000ffff	0000000000
DMA_ENABLE	0x7e007ff0	RW	15	0x00007fff	0x00007fff

Unsupported defines

define	value
DMA_CB_2DSTR(n)	MACRO
DMA_CB_ADDR(n)	MACRO
DMA_CB_DA(n)	MACRO
DMA_CB_NEXT(n)	MACRO
DMA_CB_SA(n)	MACRO
DMA_CB_TI(n)	MACRO
DMA_CB_TL(n)	MACRO
DMA_CH_BASE(n)	MACRO
DMA_CS(n)	MACRO
DMA_CS_ABORT	0x40000000
DMA_CS_ACTIVE	1
DMA_CS_DIS_DBS_PAUSE	0x20000000
DMA_CS_DREQ	8
DMA_CS_DREQ_PAUSED	32
DMA_CS_END	2
DMA_CS_ERROR	256
DMA_CS_INT	4
DMA_CS_PANIC_PRIORITY	0x100000
DMA_CS_PAUSED	16
DMA_CS_PRIORITY	0x10000
DMA_CS_RESET	0x80000000
DMA_CS_WAITING_FOR_LAST_WRITE	64
DMA_CS_WAIT_FOR_LAST_WRITE	0x10000000
DMA_DEBUG(n)	MACRO
DMA_DEBUG_FIFO_ERR	2
DMA_DEBUG_ID	256
DMA_DEBUG_OUTSTANDING_WRITES	16
DMA_DEBUG_READ_ERR	4
DMA_DEBUG_READ_LAST_ERR	(0)
DMA_DEBUG_STATE	0x10000
DMA_DEBUG_VERSION	0x2000000
DMA_INTERRUPT(n)	MACRO
DMA_REG(n,offset)	MACRO
DMA_TI_BURST_N(n)	MACRO
DMA_TI_D_128	32
DMA_TI_D_32	0
DMA_TI_D_DREQ	64
DMA_TI_D_IGNORE	128
DMA_TI_D_INC	16
DMA_TI_D_WIDTH	32
DMA_TI_INT	1
DMA_TI_NO_WIDE_BURSTS	0x4000000
DMA_TI_PERMAP	0x10000
DMA_TI_PER_MAP(n)	MACRO
DMA_TI_S_128	0x200
DMA_TI_S_32	0
DMA_TI_S_DREQ	0x400
DMA_TI_S_IGNORE	0x800
DMA_TI_S_INC	256
DMA_TI_S_WIDTH	0x200
DMA_TI_TDMODE	2
DMA_TI_WAITS(n)	MACRO
DMA_TI_WAIT_RESP	8

Register:DMA_INT_STATUS (0x7e007fe0)

field_name	start_bit	end_bit	set	clear	reset
DMA_INT_STATUS_INT0	0	0	0x00000001	0xfffffffe	0x0
DMA_INT_STATUS_INT1	1	1	0x00000002	0xfffffffd	0x0
DMA_INT_STATUS_INT2	2	2	0x00000004	0xfffffffb	0x0
DMA_INT_STATUS_INT3	3	3	0x00000008	0xfffffff7	0x0
DMA_INT_STATUS_INT4	4	4	0x00000010	0xffffffef	0x0
DMA_INT_STATUS_INT5	5	5	0x00000020	0xffffffdf	0x0
DMA_INT_STATUS_INT6	6	6	0x00000040	0xffffffbf	0x0
DMA_INT_STATUS_INT7	7	7	0x00000080	0xffffff7f	0x0
DMA_INT_STATUS_INT8	8	8	0x00000100	0xfffffeff	0x0
DMA_INT_STATUS_INT9	9	9	0x00000200	0xfffffdff	0x0
DMA_INT_STATUS_INT10	10	10	0x00000400	0xfffffbff	0x0
DMA_INT_STATUS_INT11	11	11	0x00000800	0xfffff7ff	0x0
DMA_INT_STATUS_INT12	12	12	0x00001000	0xffffefff	0x0
DMA_INT_STATUS_INT13	13	13	0x00002000	0xffffdfff	0x0
DMA_INT_STATUS_INT14	14	14	0x00004000	0xffffbfff	0x0
DMA_INT_STATUS_INT15	15	15	0x00008000	0xffff7fff	0x0

Register:DMA_ENABLE (0x7e007ff0)

field_name	start_bit	end_bit	set	clear	reset
DMA_ENABLE_EN0	0	0	0x00000001	0xfffffffe	0x1
DMA_ENABLE_EN1	1	1	0x00000002	0xfffffffd	0x1
DMA_ENABLE_EN2	2	2	0x00000004	0xfffffffb	0x1
DMA_ENABLE_EN3	3	3	0x00000008	0xfffffff7	0x1
DMA_ENABLE_EN4	4	4	0x00000010	0xffffffef	0x1
DMA_ENABLE_EN5	5	5	0x00000020	0xffffffdf	0x1
DMA_ENABLE_EN6	6	6	0x00000040	0xffffffbf	0x1
DMA_ENABLE_EN7	7	7	0x00000080	0xffffff7f	0x1
DMA_ENABLE_EN8	8	8	0x00000100	0xfffffeff	0x1
DMA_ENABLE_EN9	9	9	0x00000200	0xfffffdff	0x1
DMA_ENABLE_EN10	10	10	0x00000400	0xfffffbff	0x1
DMA_ENABLE_EN11	11	11	0x00000800	0xfffff7ff	0x1
DMA_ENABLE_EN12	12	12	0x00001000	0xffffefff	0x1
DMA_ENABLE_EN13	13	13	0x00002000	0xffffdfff	0x1
DMA_ENABLE_EN14	14	14	0x00004000	0xffffbfff	0x1

DMA0

Info

base	0x7e007000

Registers

register name	address	type	width	mask	reset
DMA0_CS	0x7e007000	RW	32	0xf0ff017f	0000000000
DMA0_CONBLK_AD	0x7e007004	RW	32	0xffffffe0	0000000000
DMA0_TI	0x7e007008	RO	27	0x07fffffb
DMA0_SOURCE_AD	0x7e00700c	RO	32	0xffffffff
DMA0_DEST_AD	0x7e007010	RO	32	0xffffffff
DMA0_TXFR_LEN	0x7e007014	RO	30	0x3fffffff
DMA0_STRIDE	0x7e007018	RO	32	0xffffffff
DMA0_NEXTCONBK	0x7e00701c	RO	32	0xffffffe0
DMA0_DEBUG	0x7e007020	RW	29	0x1ffffff7	0000000000

Register:DMA0_CS (0x7e007000)

field_name	start_bit	end_bit	set	clear	reset
DMA0_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA0_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA0_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA0_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA0_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA0_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA0_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA0_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA0_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA0_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA0_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA0_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA0_CONBLK_AD (0x7e007004)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA0_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA0_TI (0x7e007008)

field_name	start_bit	end_bit	set	clear	reset
DMA0_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA0_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA0_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA0_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA0_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA0_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA0_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA0_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA0_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA0_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA0_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA0_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA0_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA0_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA0_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA0_SOURCE_AD (0x7e00700c)

field_name	start_bit	end_bit	set	clear	reset
DMA0_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA0_DEST_AD (0x7e007010)

field_name	start_bit	end_bit	set	clear	reset
DMA0_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA0_TXFR_LEN (0x7e007014)

field_name	start_bit	end_bit	set	clear	reset
DMA0_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA0_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA0_STRIDE (0x7e007018)

field_name	start_bit	end_bit	set	clear	reset
DMA0_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA0_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA0_NEXTCONBK (0x7e00701c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA0_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA0_DEBUG (0x7e007020)

field_name	start_bit	end_bit	set	clear	reset
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA0_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA0_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA0_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA0_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA0_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA0_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA0_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA1

Info

base	0x7e007100

Registers

register name	address	type	width	mask	reset
DMA1_CS	0x7e007100	RW	32	0xf0ff017f	0000000000
DMA1_CONBLK_AD	0x7e007104	RW	32	0xffffffe0	0000000000
DMA1_TI	0x7e007108	RO	27	0x07fffffb
DMA1_SOURCE_AD	0x7e00710c	RO	32	0xffffffff
DMA1_DEST_AD	0x7e007110	RO	32	0xffffffff
DMA1_TXFR_LEN	0x7e007114	RO	30	0x3fffffff
DMA1_STRIDE	0x7e007118	RO	32	0xffffffff
DMA1_NEXTCONBK	0x7e00711c	RO	32	0xffffffe0
DMA1_DEBUG	0x7e007120	RW	29	0x1ffffff7	0000000000

Register:DMA1_CS (0x7e007100)

field_name	start_bit	end_bit	set	clear	reset
DMA1_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA1_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA1_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA1_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA1_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA1_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA1_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA1_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA1_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA1_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA1_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA1_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA1_CONBLK_AD (0x7e007104)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA1_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA1_TI (0x7e007108)

field_name	start_bit	end_bit	set	clear	reset
DMA1_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA1_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA1_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA1_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA1_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA1_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA1_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA1_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA1_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA1_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA1_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA1_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA1_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA1_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA1_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA1_SOURCE_AD (0x7e00710c)

field_name	start_bit	end_bit	set	clear	reset
DMA1_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA1_DEST_AD (0x7e007110)

field_name	start_bit	end_bit	set	clear	reset
DMA1_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA1_TXFR_LEN (0x7e007114)

field_name	start_bit	end_bit	set	clear	reset
DMA1_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA1_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA1_STRIDE (0x7e007118)

field_name	start_bit	end_bit	set	clear	reset
DMA1_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA1_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA1_NEXTCONBK (0x7e00711c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA1_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA1_DEBUG (0x7e007120)

field_name	start_bit	end_bit	set	clear	reset
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA1_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA1_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA1_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA1_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA1_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA1_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA1_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA10

Info

base	0x7e007a00

Registers

register name	address	type	width	mask	reset
DMA10_CS	0x7e007a00	RW	32	0xf0ff017f	0000000000
DMA10_CONBLK_AD	0x7e007a04	RW	32	0xffffffe0	0000000000
DMA10_TI	0x7e007a08	RO	26	0x03fffff9
DMA10_SOURCE_AD	0x7e007a0c	RO	32	0xffffffff
DMA10_DEST_AD	0x7e007a10	RO	32	0xffffffff
DMA10_TXFR_LEN	0x7e007a14	RO	16	0x0000ffff
DMA10_NEXTCONBK	0x7e007a1c	RO	32	0xffffffe0
DMA10_DEBUG	0x7e007a20	RW	29	0x1ffffff7	0000000000

Register:DMA10_CS (0x7e007a00)

field_name	start_bit	end_bit	set	clear	reset
DMA10_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA10_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA10_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA10_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA10_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA10_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA10_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA10_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA10_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA10_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA10_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA10_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA10_CONBLK_AD (0x7e007a04)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA10_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA10_TI (0x7e007a08)

field_name	start_bit	end_bit	set	clear	reset
DMA10_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA10_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA10_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA10_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA10_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA10_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA10_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA10_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA10_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA10_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA10_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA10_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA10_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA10_SOURCE_AD (0x7e007a0c)

field_name	start_bit	end_bit	set	clear	reset
DMA10_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA10_DEST_AD (0x7e007a10)

field_name	start_bit	end_bit	set	clear	reset
DMA10_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA10_TXFR_LEN (0x7e007a14)

field_name	start_bit	end_bit	set	clear	reset
DMA10_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA10_NEXTCONBK (0x7e007a1c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA10_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA10_DEBUG (0x7e007a20)

field_name	start_bit	end_bit	set	clear	reset
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA10_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA10_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA10_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA10_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA10_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA10_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA10_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA11

Info

base	0x7e007b00

Registers

register name	address	type	width	mask	reset
DMA11_CS	0x7e007b00	RW	32	0xf0ff017f	0000000000
DMA11_CONBLK_AD	0x7e007b04	RW	32	0xffffffe0	0000000000
DMA11_TI	0x7e007b08	RO	26	0x03fffff9
DMA11_SOURCE_AD	0x7e007b0c	RO	32	0xffffffff
DMA11_DEST_AD	0x7e007b10	RO	32	0xffffffff
DMA11_TXFR_LEN	0x7e007b14	RO	16	0x0000ffff
DMA11_NEXTCONBK	0x7e007b1c	RO	32	0xffffffe0
DMA11_DEBUG	0x7e007b20	RW	29	0x1ffffff7	0000000000

Register:DMA11_CS (0x7e007b00)

field_name	start_bit	end_bit	set	clear	reset
DMA11_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA11_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA11_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA11_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA11_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA11_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA11_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA11_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA11_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA11_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA11_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA11_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA11_CONBLK_AD (0x7e007b04)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA11_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA11_TI (0x7e007b08)

field_name	start_bit	end_bit	set	clear	reset
DMA11_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA11_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA11_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA11_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA11_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA11_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA11_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA11_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA11_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA11_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA11_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA11_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA11_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA11_SOURCE_AD (0x7e007b0c)

field_name	start_bit	end_bit	set	clear	reset
DMA11_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA11_DEST_AD (0x7e007b10)

field_name	start_bit	end_bit	set	clear	reset
DMA11_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA11_TXFR_LEN (0x7e007b14)

field_name	start_bit	end_bit	set	clear	reset
DMA11_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA11_NEXTCONBK (0x7e007b1c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA11_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA11_DEBUG (0x7e007b20)

field_name	start_bit	end_bit	set	clear	reset
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA11_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA11_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA11_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA11_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA11_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA11_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA11_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA12

Info

base	0x7e007c00

Registers

register name	address	type	width	mask	reset
DMA12_CS	0x7e007c00	RW	32	0xf0ff017f	0000000000
DMA12_CONBLK_AD	0x7e007c04	RW	32	0xffffffe0	0000000000
DMA12_TI	0x7e007c08	RO	26	0x03fffff9
DMA12_SOURCE_AD	0x7e007c0c	RO	32	0xffffffff
DMA12_DEST_AD	0x7e007c10	RO	32	0xffffffff
DMA12_TXFR_LEN	0x7e007c14	RO	16	0x0000ffff
DMA12_NEXTCONBK	0x7e007c1c	RO	32	0xffffffe0
DMA12_DEBUG	0x7e007c20	RW	29	0x1ffffff7	0000000000

Register:DMA12_CS (0x7e007c00)

field_name	start_bit	end_bit	set	clear	reset
DMA12_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA12_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA12_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA12_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA12_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA12_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA12_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA12_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA12_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA12_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA12_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA12_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA12_CONBLK_AD (0x7e007c04)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA12_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA12_TI (0x7e007c08)

field_name	start_bit	end_bit	set	clear	reset
DMA12_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA12_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA12_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA12_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA12_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA12_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA12_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA12_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA12_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA12_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA12_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA12_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA12_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA12_SOURCE_AD (0x7e007c0c)

field_name	start_bit	end_bit	set	clear	reset
DMA12_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA12_DEST_AD (0x7e007c10)

field_name	start_bit	end_bit	set	clear	reset
DMA12_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA12_TXFR_LEN (0x7e007c14)

field_name	start_bit	end_bit	set	clear	reset
DMA12_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA12_NEXTCONBK (0x7e007c1c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA12_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA12_DEBUG (0x7e007c20)

field_name	start_bit	end_bit	set	clear	reset
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA12_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA12_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA12_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA12_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA12_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA12_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA12_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA13

Info

base	0x7e007d00

Registers

register name	address	type	width	mask	reset
DMA13_CS	0x7e007d00	RW	32	0xf0ff017f	0000000000
DMA13_CONBLK_AD	0x7e007d04	RW	32	0xffffffe0	0000000000
DMA13_TI	0x7e007d08	RO	26	0x03fffff9
DMA13_SOURCE_AD	0x7e007d0c	RO	32	0xffffffff
DMA13_DEST_AD	0x7e007d10	RO	32	0xffffffff
DMA13_TXFR_LEN	0x7e007d14	RO	16	0x0000ffff
DMA13_NEXTCONBK	0x7e007d1c	RO	32	0xffffffe0
DMA13_DEBUG	0x7e007d20	RW	29	0x1ffffff7	0000000000

Register:DMA13_CS (0x7e007d00)

field_name	start_bit	end_bit	set	clear	reset
DMA13_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA13_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA13_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA13_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA13_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA13_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA13_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA13_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA13_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA13_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA13_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA13_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA13_CONBLK_AD (0x7e007d04)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA13_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA13_TI (0x7e007d08)

field_name	start_bit	end_bit	set	clear	reset
DMA13_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA13_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA13_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA13_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA13_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA13_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA13_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA13_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA13_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA13_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA13_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA13_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA13_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA13_SOURCE_AD (0x7e007d0c)

field_name	start_bit	end_bit	set	clear	reset
DMA13_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA13_DEST_AD (0x7e007d10)

field_name	start_bit	end_bit	set	clear	reset
DMA13_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA13_TXFR_LEN (0x7e007d14)

field_name	start_bit	end_bit	set	clear	reset
DMA13_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA13_NEXTCONBK (0x7e007d1c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA13_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA13_DEBUG (0x7e007d20)

field_name	start_bit	end_bit	set	clear	reset
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA13_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA13_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA13_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA13_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA13_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA13_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA13_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA14

Info

base	0x7e007e00

Registers

register name	address	type	width	mask	reset
DMA14_CS	0x7e007e00	RW	32	0xf0ff017f	0000000000
DMA14_CONBLK_AD	0x7e007e04	RW	32	0xffffffe0	0000000000
DMA14_TI	0x7e007e08	RO	26	0x03fffff9
DMA14_SOURCE_AD	0x7e007e0c	RO	32	0xffffffff
DMA14_DEST_AD	0x7e007e10	RO	32	0xffffffff
DMA14_TXFR_LEN	0x7e007e14	RO	16	0x0000ffff
DMA14_NEXTCONBK	0x7e007e1c	RO	32	0xffffffe0
DMA14_DEBUG	0x7e007e20	RW	29	0x1ffffff7	0000000000

Register:DMA14_CS (0x7e007e00)

field_name	start_bit	end_bit	set	clear	reset
DMA14_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA14_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA14_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA14_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA14_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA14_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA14_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA14_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA14_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA14_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA14_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA14_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA14_CONBLK_AD (0x7e007e04)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA14_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA14_TI (0x7e007e08)

field_name	start_bit	end_bit	set	clear	reset
DMA14_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA14_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA14_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA14_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA14_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA14_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA14_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA14_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA14_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA14_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA14_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA14_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA14_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA14_SOURCE_AD (0x7e007e0c)

field_name	start_bit	end_bit	set	clear	reset
DMA14_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA14_DEST_AD (0x7e007e10)

field_name	start_bit	end_bit	set	clear	reset
DMA14_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA14_TXFR_LEN (0x7e007e14)

field_name	start_bit	end_bit	set	clear	reset
DMA14_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA14_NEXTCONBK (0x7e007e1c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA14_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA14_DEBUG (0x7e007e20)

field_name	start_bit	end_bit	set	clear	reset
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA14_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA14_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA14_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA14_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA14_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA14_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA14_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA15

Info

base	0x7ee05000

Registers

register name	address	type	width	mask	reset
DMA15_CS	0x7ee05000	RW	32	0xf0ff017f	0000000000
DMA15_CONBLK_AD	0x7ee05004	RW	32	0xffffffe0	0000000000
DMA15_TI	0x7ee05008	RO	27	0x07fffffb
DMA15_SOURCE_AD	0x7ee0500c	RO	32	0xffffffff
DMA15_DEST_AD	0x7ee05010	RO	32	0xffffffff
DMA15_TXFR_LEN	0x7ee05014	RO	30	0x3fffffff
DMA15_STRIDE	0x7ee05018	RO	32	0xffffffff
DMA15_NEXTCONBK	0x7ee0501c	RO	32	0xffffffe0
DMA15_DEBUG	0x7ee05020	RW	29	0x1ffffff7	0000000000

Register:DMA15_CS (0x7ee05000)

field_name	start_bit	end_bit	set	clear	reset
DMA15_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA15_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA15_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA15_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA15_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA15_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA15_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA15_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA15_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA15_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA15_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA15_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA15_CONBLK_AD (0x7ee05004)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA15_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA15_TI (0x7ee05008)

field_name	start_bit	end_bit	set	clear	reset
DMA15_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA15_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA15_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA15_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA15_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA15_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA15_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA15_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA15_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA15_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA15_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA15_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA15_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA15_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA15_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA15_SOURCE_AD (0x7ee0500c)

field_name	start_bit	end_bit	set	clear	reset
DMA15_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA15_DEST_AD (0x7ee05010)

field_name	start_bit	end_bit	set	clear	reset
DMA15_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA15_TXFR_LEN (0x7ee05014)

field_name	start_bit	end_bit	set	clear	reset
DMA15_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA15_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA15_STRIDE (0x7ee05018)

field_name	start_bit	end_bit	set	clear	reset
DMA15_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA15_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA15_NEXTCONBK (0x7ee0501c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA15_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA15_DEBUG (0x7ee05020)

field_name	start_bit	end_bit	set	clear	reset
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA15_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA15_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA15_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA15_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA15_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA15_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA15_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA2

Info

base	0x7e007200

Registers

register name	address	type	width	mask	reset
DMA2_CS	0x7e007200	RW	32	0xf0ff017f	0000000000
DMA2_CONBLK_AD	0x7e007204	RW	32	0xffffffe0	0000000000
DMA2_TI	0x7e007208	RO	27	0x07fffffb
DMA2_SOURCE_AD	0x7e00720c	RO	32	0xffffffff
DMA2_DEST_AD	0x7e007210	RO	32	0xffffffff
DMA2_TXFR_LEN	0x7e007214	RO	30	0x3fffffff
DMA2_STRIDE	0x7e007218	RO	32	0xffffffff
DMA2_NEXTCONBK	0x7e00721c	RO	32	0xffffffe0
DMA2_DEBUG	0x7e007220	RW	29	0x1ffffff7	0000000000

Register:DMA2_CS (0x7e007200)

field_name	start_bit	end_bit	set	clear	reset
DMA2_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA2_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA2_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA2_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA2_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA2_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA2_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA2_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA2_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA2_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA2_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA2_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA2_CONBLK_AD (0x7e007204)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA2_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA2_TI (0x7e007208)

field_name	start_bit	end_bit	set	clear	reset
DMA2_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA2_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA2_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA2_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA2_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA2_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA2_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA2_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA2_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA2_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA2_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA2_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA2_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA2_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA2_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA2_SOURCE_AD (0x7e00720c)

field_name	start_bit	end_bit	set	clear	reset
DMA2_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA2_DEST_AD (0x7e007210)

field_name	start_bit	end_bit	set	clear	reset
DMA2_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA2_TXFR_LEN (0x7e007214)

field_name	start_bit	end_bit	set	clear	reset
DMA2_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA2_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA2_STRIDE (0x7e007218)

field_name	start_bit	end_bit	set	clear	reset
DMA2_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA2_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA2_NEXTCONBK (0x7e00721c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA2_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA2_DEBUG (0x7e007220)

field_name	start_bit	end_bit	set	clear	reset
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA2_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA2_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA2_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA2_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA2_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA2_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA2_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA3

Info

base	0x7e007300

Registers

register name	address	type	width	mask	reset
DMA3_CS	0x7e007300	RW	32	0xf0ff017f	0000000000
DMA3_CONBLK_AD	0x7e007304	RW	32	0xffffffe0	0000000000
DMA3_TI	0x7e007308	RO	27	0x07fffffb
DMA3_SOURCE_AD	0x7e00730c	RO	32	0xffffffff
DMA3_DEST_AD	0x7e007310	RO	32	0xffffffff
DMA3_TXFR_LEN	0x7e007314	RO	30	0x3fffffff
DMA3_STRIDE	0x7e007318	RO	32	0xffffffff
DMA3_NEXTCONBK	0x7e00731c	RO	32	0xffffffe0
DMA3_DEBUG	0x7e007320	RW	29	0x1ffffff7	0000000000

Register:DMA3_CS (0x7e007300)

field_name	start_bit	end_bit	set	clear	reset
DMA3_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA3_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA3_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA3_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA3_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA3_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA3_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA3_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA3_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA3_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA3_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA3_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA3_CONBLK_AD (0x7e007304)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA3_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA3_TI (0x7e007308)

field_name	start_bit	end_bit	set	clear	reset
DMA3_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA3_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA3_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA3_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA3_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA3_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA3_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA3_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA3_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA3_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA3_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA3_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA3_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA3_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA3_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA3_SOURCE_AD (0x7e00730c)

field_name	start_bit	end_bit	set	clear	reset
DMA3_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA3_DEST_AD (0x7e007310)

field_name	start_bit	end_bit	set	clear	reset
DMA3_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA3_TXFR_LEN (0x7e007314)

field_name	start_bit	end_bit	set	clear	reset
DMA3_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA3_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA3_STRIDE (0x7e007318)

field_name	start_bit	end_bit	set	clear	reset
DMA3_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA3_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA3_NEXTCONBK (0x7e00731c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA3_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA3_DEBUG (0x7e007320)

field_name	start_bit	end_bit	set	clear	reset
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA3_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA3_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA3_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA3_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA3_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA3_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA3_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA4

Info

base	0x7e007400

Registers

register name	address	type	width	mask	reset
DMA4_CS	0x7e007400	RW	32	0xf0ff017f	0000000000
DMA4_CONBLK_AD	0x7e007404	RW	32	0xffffffe0	0000000000
DMA4_TI	0x7e007408	RO	27	0x07fffffb
DMA4_SOURCE_AD	0x7e00740c	RO	32	0xffffffff
DMA4_DEST_AD	0x7e007410	RO	32	0xffffffff
DMA4_TXFR_LEN	0x7e007414	RO	30	0x3fffffff
DMA4_STRIDE	0x7e007418	RO	32	0xffffffff
DMA4_NEXTCONBK	0x7e00741c	RO	32	0xffffffe0
DMA4_DEBUG	0x7e007420	RW	29	0x1ffffff7	0000000000

Register:DMA4_CS (0x7e007400)

field_name	start_bit	end_bit	set	clear	reset
DMA4_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA4_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA4_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA4_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA4_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA4_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA4_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA4_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA4_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA4_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA4_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA4_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA4_CONBLK_AD (0x7e007404)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA4_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA4_TI (0x7e007408)

field_name	start_bit	end_bit	set	clear	reset
DMA4_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA4_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA4_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA4_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA4_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA4_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA4_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA4_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA4_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA4_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA4_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA4_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA4_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA4_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA4_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA4_SOURCE_AD (0x7e00740c)

field_name	start_bit	end_bit	set	clear	reset
DMA4_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA4_DEST_AD (0x7e007410)

field_name	start_bit	end_bit	set	clear	reset
DMA4_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA4_TXFR_LEN (0x7e007414)

field_name	start_bit	end_bit	set	clear	reset
DMA4_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA4_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA4_STRIDE (0x7e007418)

field_name	start_bit	end_bit	set	clear	reset
DMA4_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA4_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA4_NEXTCONBK (0x7e00741c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA4_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA4_DEBUG (0x7e007420)

field_name	start_bit	end_bit	set	clear	reset
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA4_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA4_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA4_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA4_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA4_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA4_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA4_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA5

Info

base	0x7e007500

Registers

register name	address	type	width	mask	reset
DMA5_CS	0x7e007500	RW	32	0xf0ff017f	0000000000
DMA5_CONBLK_AD	0x7e007504	RW	32	0xffffffe0	0000000000
DMA5_TI	0x7e007508	RO	27	0x07fffffb
DMA5_SOURCE_AD	0x7e00750c	RO	32	0xffffffff
DMA5_DEST_AD	0x7e007510	RO	32	0xffffffff
DMA5_TXFR_LEN	0x7e007514	RO	30	0x3fffffff
DMA5_STRIDE	0x7e007518	RO	32	0xffffffff
DMA5_NEXTCONBK	0x7e00751c	RO	32	0xffffffe0
DMA5_DEBUG	0x7e007520	RW	29	0x1ffffff7	0000000000

Register:DMA5_CS (0x7e007500)

field_name	start_bit	end_bit	set	clear	reset
DMA5_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA5_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA5_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA5_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA5_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA5_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA5_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA5_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA5_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA5_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA5_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA5_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA5_CONBLK_AD (0x7e007504)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA5_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA5_TI (0x7e007508)

field_name	start_bit	end_bit	set	clear	reset
DMA5_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA5_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA5_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA5_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA5_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA5_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA5_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA5_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA5_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA5_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA5_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA5_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA5_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA5_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA5_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA5_SOURCE_AD (0x7e00750c)

field_name	start_bit	end_bit	set	clear	reset
DMA5_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA5_DEST_AD (0x7e007510)

field_name	start_bit	end_bit	set	clear	reset
DMA5_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA5_TXFR_LEN (0x7e007514)

field_name	start_bit	end_bit	set	clear	reset
DMA5_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA5_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA5_STRIDE (0x7e007518)

field_name	start_bit	end_bit	set	clear	reset
DMA5_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA5_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA5_NEXTCONBK (0x7e00751c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA5_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA5_DEBUG (0x7e007520)

field_name	start_bit	end_bit	set	clear	reset
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA5_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA5_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA5_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA5_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA5_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA5_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA5_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA6

Info

base	0x7e007600

Registers

register name	address	type	width	mask	reset
DMA6_CS	0x7e007600	RW	32	0xf0ff017f	0000000000
DMA6_CONBLK_AD	0x7e007604	RW	32	0xffffffe0	0000000000
DMA6_TI	0x7e007608	RO	27	0x07fffffb
DMA6_SOURCE_AD	0x7e00760c	RO	32	0xffffffff
DMA6_DEST_AD	0x7e007610	RO	32	0xffffffff
DMA6_TXFR_LEN	0x7e007614	RO	30	0x3fffffff
DMA6_STRIDE	0x7e007618	RO	32	0xffffffff
DMA6_NEXTCONBK	0x7e00761c	RO	32	0xffffffe0
DMA6_DEBUG	0x7e007620	RW	29	0x1ffffff7	0000000000

Register:DMA6_CS (0x7e007600)

field_name	start_bit	end_bit	set	clear	reset
DMA6_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA6_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA6_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA6_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA6_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA6_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA6_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA6_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA6_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA6_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA6_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA6_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA6_CONBLK_AD (0x7e007604)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA6_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA6_TI (0x7e007608)

field_name	start_bit	end_bit	set	clear	reset
DMA6_TI_INTEN	0	0	0x00000001	0xfffffffe
DMA6_TI_TDMODE	1	1	0x00000002	0xfffffffd
missing definiton	2	2	NA	NA	NA
DMA6_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA6_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA6_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA6_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA6_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA6_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA6_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA6_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA6_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA6_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA6_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA6_TI_WAITS	21	25	0x03e00000	0xfc1fffff
DMA6_TI_NO_WIDE_BURSTS	26	26	0x04000000	0xfbffffff

Register:DMA6_SOURCE_AD (0x7e00760c)

field_name	start_bit	end_bit	set	clear	reset
DMA6_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA6_DEST_AD (0x7e007610)

field_name	start_bit	end_bit	set	clear	reset
DMA6_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA6_TXFR_LEN (0x7e007614)

field_name	start_bit	end_bit	set	clear	reset
DMA6_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000
DMA6_TXFR_LEN_YLENGTH	16	29	0x3fff0000	0xc000ffff

Register:DMA6_STRIDE (0x7e007618)

field_name	start_bit	end_bit	set	clear	reset
DMA6_STRIDE_S_STRIDE	0	15	0x0000ffff	0xffff0000
DMA6_STRIDE_D_STRIDE	16	31	0xffff0000	0x0000ffff

Register:DMA6_NEXTCONBK (0x7e00761c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA6_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA6_DEBUG (0x7e007620)

field_name	start_bit	end_bit	set	clear	reset
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA6_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA6_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA6_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA6_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA6_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA6_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA6_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA7

Info

base	0x7e007700

Registers

register name	address	type	width	mask	reset
DMA7_CS	0x7e007700	RW	32	0xf0ff017f	0000000000
DMA7_CONBLK_AD	0x7e007704	RW	32	0xffffffe0	0000000000
DMA7_TI	0x7e007708	RO	26	0x03fffff9
DMA7_SOURCE_AD	0x7e00770c	RO	32	0xffffffff
DMA7_DEST_AD	0x7e007710	RO	32	0xffffffff
DMA7_TXFR_LEN	0x7e007714	RO	16	0x0000ffff
DMA7_NEXTCONBK	0x7e00771c	RO	32	0xffffffe0
DMA7_DEBUG	0x7e007720	RW	29	0x1ffffff7	0000000000

Register:DMA7_CS (0x7e007700)

field_name	start_bit	end_bit	set	clear	reset
DMA7_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA7_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA7_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA7_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA7_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA7_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA7_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA7_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA7_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA7_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA7_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA7_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA7_CONBLK_AD (0x7e007704)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA7_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA7_TI (0x7e007708)

field_name	start_bit	end_bit	set	clear	reset
DMA7_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA7_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA7_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA7_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA7_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA7_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA7_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA7_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA7_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA7_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA7_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA7_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA7_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA7_SOURCE_AD (0x7e00770c)

field_name	start_bit	end_bit	set	clear	reset
DMA7_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA7_DEST_AD (0x7e007710)

field_name	start_bit	end_bit	set	clear	reset
DMA7_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA7_TXFR_LEN (0x7e007714)

field_name	start_bit	end_bit	set	clear	reset
DMA7_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA7_NEXTCONBK (0x7e00771c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA7_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA7_DEBUG (0x7e007720)

field_name	start_bit	end_bit	set	clear	reset
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA7_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA7_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA7_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA7_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA7_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA7_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA7_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA8

Info

base	0x7e007800

Registers

register name	address	type	width	mask	reset
DMA8_CS	0x7e007800	RW	32	0xf0ff017f	0000000000
DMA8_CONBLK_AD	0x7e007804	RW	32	0xffffffe0	0000000000
DMA8_TI	0x7e007808	RO	26	0x03fffff9
DMA8_SOURCE_AD	0x7e00780c	RO	32	0xffffffff
DMA8_DEST_AD	0x7e007810	RO	32	0xffffffff
DMA8_TXFR_LEN	0x7e007814	RO	16	0x0000ffff
DMA8_NEXTCONBK	0x7e00781c	RO	32	0xffffffe0
DMA8_DEBUG	0x7e007820	RW	29	0x1ffffff7	0000000000

Register:DMA8_CS (0x7e007800)

field_name	start_bit	end_bit	set	clear	reset
DMA8_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA8_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA8_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA8_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA8_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA8_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA8_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA8_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA8_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA8_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA8_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA8_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA8_CONBLK_AD (0x7e007804)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA8_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA8_TI (0x7e007808)

field_name	start_bit	end_bit	set	clear	reset
DMA8_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA8_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA8_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA8_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA8_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA8_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA8_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA8_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA8_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA8_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA8_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA8_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA8_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA8_SOURCE_AD (0x7e00780c)

field_name	start_bit	end_bit	set	clear	reset
DMA8_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA8_DEST_AD (0x7e007810)

field_name	start_bit	end_bit	set	clear	reset
DMA8_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA8_TXFR_LEN (0x7e007814)

field_name	start_bit	end_bit	set	clear	reset
DMA8_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA8_NEXTCONBK (0x7e00781c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA8_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA8_DEBUG (0x7e007820)

field_name	start_bit	end_bit	set	clear	reset
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA8_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA8_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA8_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA8_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA8_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA8_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA8_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DMA9

Info

base	0x7e007900

Registers

register name	address	type	width	mask	reset
DMA9_CS	0x7e007900	RW	32	0xf0ff017f	0000000000
DMA9_CONBLK_AD	0x7e007904	RW	32	0xffffffe0	0000000000
DMA9_TI	0x7e007908	RO	26	0x03fffff9
DMA9_SOURCE_AD	0x7e00790c	RO	32	0xffffffff
DMA9_DEST_AD	0x7e007910	RO	32	0xffffffff
DMA9_TXFR_LEN	0x7e007914	RO	16	0x0000ffff
DMA9_NEXTCONBK	0x7e00791c	RO	32	0xffffffe0
DMA9_DEBUG	0x7e007920	RW	29	0x1ffffff7	0000000000

Register:DMA9_CS (0x7e007900)

field_name	start_bit	end_bit	set	clear	reset
DMA9_CS_ACTIVE	0	0	0x00000001	0xfffffffe	0x0
DMA9_CS_END	1	1	0x00000002	0xfffffffd	0x0
DMA9_CS_INT	2	2	0x00000004	0xfffffffb	0x0
DMA9_CS_DREQ	3	3	0x00000008	0xfffffff7	0x0
DMA9_CS_PAUSED	4	4	0x00000010	0xffffffef	0x0
DMA9_CS_DREQ_STOPS_DMA	5	5	0x00000020	0xffffffdf	0x0
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DMA9_CS_ERROR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	15	NA	NA	NA
DMA9_CS_PRIORITY	16	19	0x000f0000	0xfff0ffff	0x0
DMA9_CS_PANIC_PRIORITY	20	23	0x00f00000	0xff0fffff	0x0
missing definiton	24	27	NA	NA	NA
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES	28	28	0x10000000	0xefffffff	0x0
DMA9_CS_DISDEBUG	29	29	0x20000000	0xdfffffff	0x0
DMA9_CS_ABORT	30	30	0x40000000	0xbfffffff	0x0
DMA9_CS_RESET	31	31	0x80000000	0x7fffffff	0x0

Register:DMA9_CONBLK_AD (0x7e007904)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA9_CONBLK_AD_SCB_ADDR	5	31	0xffffffe0	0x0000001f	0x0

Register:DMA9_TI (0x7e007908)

field_name	start_bit	end_bit	set	clear	reset
DMA9_TI_INTEN	0	0	0x00000001	0xfffffffe
missing definiton	1	2	NA	NA	NA
DMA9_TI_WAIT_RESP	3	3	0x00000008	0xfffffff7
DMA9_TI_DEST_INC	4	4	0x00000010	0xffffffef
DMA9_TI_DEST_WIDTH	5	5	0x00000020	0xffffffdf
DMA9_TI_DEST_DREQ	6	6	0x00000040	0xffffffbf
DMA9_TI_DEST_IGNORE	7	7	0x00000080	0xffffff7f
DMA9_TI_SRC_INC	8	8	0x00000100	0xfffffeff
DMA9_TI_SRC_WIDTH	9	9	0x00000200	0xfffffdff
DMA9_TI_SRC_DREQ	10	10	0x00000400	0xfffffbff
DMA9_TI_SRC_IGNORE	11	11	0x00000800	0xfffff7ff
DMA9_TI_BURST_LENGTH	12	15	0x0000f000	0xffff0fff
DMA9_TI_PERMAP	16	20	0x001f0000	0xffe0ffff
DMA9_TI_WAITS	21	25	0x03e00000	0xfc1fffff

Register:DMA9_SOURCE_AD (0x7e00790c)

field_name	start_bit	end_bit	set	clear	reset
DMA9_SOURCE_AD_S_ADDR	0	31	0xffffffff	0x00000000

Register:DMA9_DEST_AD (0x7e007910)

field_name	start_bit	end_bit	set	clear	reset
DMA9_DEST_AD_D_ADDR	0	31	0xffffffff	0x00000000

Register:DMA9_TXFR_LEN (0x7e007914)

field_name	start_bit	end_bit	set	clear	reset
DMA9_TXFR_LEN_XLENGTH	0	15	0x0000ffff	0xffff0000

Register:DMA9_NEXTCONBK (0x7e00791c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	4	NA	NA	NA
DMA9_NEXTCONBK_ADDR	5	31	0xffffffe0	0x0000001f

Register:DMA9_DEBUG (0x7e007920)

field_name	start_bit	end_bit	set	clear	reset
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR	0	0	0x00000001	0xfffffffe	0x0
DMA9_DEBUG_FIFO_ERROR	1	1	0x00000002	0xfffffffd	0x0
DMA9_DEBUG_READ_ERROR	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DMA9_DEBUG_OUTSTANDING_WRITES	4	7	0x000000f0	0xffffff0f	0x0
DMA9_DEBUG_DMA_ID	8	15	0x0000ff00	0xffff00ff	0x0
DMA9_DEBUG_DMA_STATE	16	24	0x01ff0000	0xfe00ffff	0x0
DMA9_DEBUG_VERSION	25	27	0x0e000000	0xf1ffffff	0x0
DMA9_DEBUG_LITE	28	28	0x10000000	0xefffffff	0x0

DPHY_CSR

Info

description	SDRAM Data (pin) control
base	0x7ee07000

Registers

register name	address	type	width	mask	reset
DPHY_CSR_DQ_REV_ID	0x7ee07000	RW
DPHY_CSR_GLBL_DQ_DLL_RESET	0x7ee07004	RW
DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE	0x7ee07008	RW
DPHY_CSR_GLBL_DQ_DLL_CNTRL	0x7ee0700c	RW
DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL	0x7ee07010	RW
DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN	0x7ee07014	RW
DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT	0x7ee07018	RW
DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET	0x7ee0701c	RW
DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET	0x7ee07020	RW
DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET	0x7ee07024	RW
DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET	0x7ee07028	RW
DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT	0x7ee0702c	RW
DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT	0x7ee07030	RW
DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT	0x7ee07034	RW
DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT	0x7ee07038	RW
DPHY_CSR_NORM_READ_DQS_GATE_CTRL	0x7ee0703c	RW
DPHY_CSR_BOOT_READ_DQS_GATE_CTRL	0x7ee07040	RW
DPHY_CSR_PHY_FIFO_PNTRS	0x7ee07044	RW
DPHY_CSR_DQ_PHY_MISC_CTRL	0x7ee07048	RW
DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL	0x7ee0704c	RW
DPHY_CSR_DQ_PAD_MISC_CTRL	0x7ee07050	RW
DPHY_CSR_DQ_PVT_COMP_CTRL	0x7ee07054	RW
DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL	0x7ee07058	RW
DPHY_CSR_DQ_PVT_COMP_STATUS	0x7ee0705c	RW
DPHY_CSR_DQ_PVT_COMP_DEBUG	0x7ee07060	RW
DPHY_CSR_DQ_PHY_READ_CTRL	0x7ee07064	RW
DPHY_CSR_DQ_PHY_READ_STATUS	0x7ee07068	RW
DPHY_CSR_DQ_SPR_RW	0x7ee0706c	RW
DPHY_CSR_DQ_SPR1_RO	0x7ee07070	RW
DPHY_CSR_DQ_SPR_RO	0x7ee07074	RW
DPHY_CSR_CRC_CTRL	0x7ee07800	RW	9	0x00000111	0000000000
DPHY_CSR_CRC_DATA	0x7ee07804	RW	28	0x0fffffff	0000000000

DPI

Info

base	0x7e208000
id	0x44504920

Registers

register name	address	type	width	mask	reset
DPI_DPIC	DPI_BASE_ADDRESS + 0x00	RW
DPI_C	0x7e208000	RW	16	0x0000ffff	0x00003000

DSI

Info

base	0x7e209000

Registers

register name	address	type
DSI_CTRL	0x7e209000	RW
DSI_CMD_PKTC	0x7e209004	RW
DSI_CMD_PKTH	0x7e209008	RW
DSI_RX1_PKTH	0x7e20900c	RW
DSI_RX2_PKTH	0x7e209010	RW
DSI_CMD_DATA_FIFO	0x7e209014	RW
DSI_DISP0_CTRL	0x7e209018	RW
DSI_DISP1_CTRL	0x7e20901c	RW
DSI_PIX_FIFO	0x7e209020	RW
DSI_INT_STATUS	0x7e209024	RW
DSI_INT_ENABLE	0x7e209028	RW
DSI_STAT	0x7e20902c	RW
DSI_HSTX_TO_CNT	0x7e209030	RW
DSI_LPRX_TO_CNT	0x7e209034	RW
DSI_TA_TO_CNT	0x7e209038	RW
DSI_PR_TO_CNT	0x7e20903c	RW
DSI_PHY_CONTROL	0x7e209040	RW
DSI_HS_CLT0	0x7e209044	RW
DSI_HS_CLT1	0x7e209048	RW
DSI_HS_CLT2	0x7e20904c	RW
DSI_HS_DLT3	0x7e209050	RW
DSI_HS_DLT4	0x7e209054	RW
DSI_HS_DLT5	0x7e209058	RW
DSI_LP_DLT6	0x7e20905c	RW
DSI_LP_DLT7	0x7e209060	RW
DSI_AFEC0	0x7e209064	RW
DSI_AFEC1	0x7e209068	RW
DSI_TST_SEL	0x7e20906c	RW
DSI_TST_MON	0x7e209070	RW

Unsupported defines

define	value
DSI_DMA	0x10000

DSI0

Info

base	0x7e209000
id	0x00647369

Registers

register name	address	type	width	mask	reset
DSI0_CTRL	0x7e209000	RW	3	0x00000007	0000000000
DSI0_CMD_PKTC	0x7e209004	RW	32	0xffffffff	0000000000
DSI0_CMD_PKTH	0x7e209008	RW	32	0xffffffff	0000000000
DSI0_RX1_PKTH	0x7e20900c	RO	32	0xffffffff
DSI0_RX2_PKTH	0x7e209010	RO	32	0xffffffff
DSI0_CMD_DATAF	0x7e209014	RW	8	0x000000ff
DSI0_DISP0_CTR	0x7e209018	RW	32	0xffffffff	0000000000
DSI0_DISP1_CTR	0x7e20901c	RW	32	0xffffffff	0000000000
DSI0_PIX_FIFO	0x7e209020	RW	32	0xffffffff
DSI0_INT_STAT	0x7e209024	RW	32	0xffffffff
DSI0_INT_EN	0x7e209028	RW	28	0x0fffffff	0000000000
DSI0_STAT	0x7e20902c	RW	32	0xffffffff
DSI0_HSTX_TO_C	0x7e209030	RW	24	0x00ffffff	0000000000
DSI0_LPRX_TO_C	0x7e209034	RW	32	0xffffffff	0000000000
DSI0_TA_TO_CNT	0x7e209038	RW	32	0xffffffff	0000000000
DSI0_PR_TO_CNT	0x7e20903c	RW	32	0xffffffff	0000000000
DSI0_PHYC	0x7e209040	RW	18	0x0003f777	0000000000
DSI0_HS_CLT0	0x7e209044	RW	32	0xfffffffc	0000000000
DSI0_HS_CLT1	0x7e209048	RW	10	0x000003fc	0000000000
DSI0_HS_CLT2	0x7e20904c	RW	10	0x000003fc	0000000000
DSI0_HS_DLT3	0x7e209050	RW	10	0x000003fc	0000000000
DSI0_HS_DLT4	0x7e209054	RW	10	0x000003fc	0000000000
DSI0_HS_DLT5	0x7e209058	RW	10	0x000003fc	0000000000
DSI0_LP_DLT6	0x7e20905c	RW	10	0x000003fc	0000000000
DSI0_LP_DLT7	0x7e209060	RW	10	0x000003fc	0000000000
DSI0_PHY_AFEC0	0x7e209064	RW	8	0x000000ff	0000000000
DSI0_PHY_AFEC1	0x7e209068	RW	32	0xffffffff	0000000000
DSI0_TST_SEL	0x7e20906c	RW	8	0x000000ff	0000000000
DSI0_TST_MON	0x7e209070	RW	8	0x000000ff	0000000000

Register:DSI0_CTRL (0x7e209000)

field_name	start_bit	end_bit	set	clear	reset
DSI0_CTRL_CTRL0	0	0	0x00000001	0xfffffffe	0x0
DSI0_CTRL_CTRL1	1	1	0x00000002	0xfffffffd	0x0
DSI0_CTRL_CTRL2	2	2	0x00000004	0xfffffffb	0x0

Register:DSI0_PHYC (0x7e209040)

field_name	start_bit	end_bit	set	clear	reset
DSI0_PHYC_dlane_hsen_0_sync	0	0	0x00000001	0xfffffffe	0x0
DSI0_PHYC_txulpshs_0_sync	1	1	0x00000002	0xfffffffd	0x0
DSI0_PHYC_forcehsstop_sync	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
DSI0_PHYC_unused	4	4	0x00000010	0xffffffef	0x0
DSI0_PHYC_dlane_hsen_1_sync	5	5	0x00000020	0xffffffdf	0x0
DSI0_PHYC_txulpshs_1_sync	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
DSI0_PHYC_clane_hsen_sync	8	8	0x00000100	0xfffffeff	0x0
DSI0_PHYC_txulps_clk_sync	9	9	0x00000200	0xfffffdff	0x0
DSI0_PHYC_txhsclk_cont_sync	10	10	0x00000400	0xfffffbff	0x0
missing definiton	11	11	NA	NA	NA
DSI0_PHYC_dsi_esc_lpdt	12	17	0x0003f000	0xfffc0fff	0x0

DSI1

Info

base	0x7e700000
id	0x64736934

Registers

register name	address	type	width	mask	reset
DSI1_CTRL	0x7e700000	RW	32	0xffffffff	0000000000
DSI1_TXPKT1_C	0x7e700004	RW	32	0xffffffff	0000000000
DSI1_TXPKT1_H	0x7e700008	RW	32	0xffffffff	0000000000
DSI1_TXPKT2_C	0x7e70000c	RW	32	0xffffffff	0000000000
DSI1_TXPKT2_H	0x7e700010	RW	32	0xffffffff	0000000000
DSI1_RXPKT1_H	0x7e700014	RO	32	0xffffffff
DSI1_RXPKT2_H	0x7e700018	RO	32	0xffffffff
DSI1_TXPKT_CMD_FIFO	0x7e70001c	RW	8	0x000000ff
DSI1_TXPKT_PIXD_FIFO	0x7e700020	RW	32	0xffffffff	0000000000
DSI1_RXPKT_FIFO	0x7e700024	RW	32	0xffffffff	0000000000
DSI1_DISP0_CTRL	0x7e700028	RW	32	0xffffffff
DSI1_DISP1_CTRL	0x7e70002c	RW	32	0xffffffff
DSI1_INT_STAT	0x7e700030	RW	32	0xffffffff
DSI1_INT_EN	0x7e700034	RW	28	0x0fffffff	0000000000
DSI1_STAT	0x7e700038	RW	32	0xffffffff
DSI1_HSTX_TO_CNT	0x7e70003c	RW	24	0x00ffffff	0000000000
DSI1_LPRX_TO_CNT	0x7e700040	RW	32	0xffffffff	0000000000
DSI1_TA_TO_CNT	0x7e700044	RW	32	0xffffffff	0000000000
DSI1_PR_TO_CNT	0x7e700048	RW	32	0xffffffff	0000000000
DSI1_PHYC	0x7e70004c	RW	32	0xffffffff	0000000000
DSI1_HS_CLT0	0x7e700050	RW	32	0xffffffff	0000000000
DSI1_HS_CLT1	0x7e700054	RW	32	0xffffffff	0000000000
DSI1_HS_CLT2	0x7e700058	RW	32	0xffffffff	0000000000
DSI1_HS_DLT3	0x7e70005c	RW	32	0xffffffff	0000000000
DSI1_HS_DLT4	0x7e700060	RW	32	0xffffffff	0000000000
DSI1_HS_DLT5	0x7e700064	RW	32	0xffffffff	0000000000
DSI1_LP_DLT6	0x7e700068	RW	32	0xffffffff	0000000000
DSI1_LP_DLT7	0x7e70006c	RW	32	0xffffffff	0000000000
DSI1_PHY_AFEC0	0x7e700070	RW	32	0xffffffff	0000000000
DSI1_PHY_AFEC1	0x7e700074	RW	32	0xffffffff	0000000000
DSI1_TST_SEL	0x7e700078	RW	32	0xffffffff	0000000000
DSI1_TST_MON	0x7e70007c	RW	32	0xffffffff	0000000000

EMMC

Info

base	0x7e300000

Registers

register name	address	type	width	mask	reset
EMMC_ARG2	0x7e300000	RW	32	0xffffffff	0000000000
EMMC_BLKSIZECNT	0x7e300004	RW	32	0xffffffff	0000000000
EMMC_ARG1	0x7e300008	RW	32	0xffffffff	0000000000
EMMC_CMDTM	0x7e30000c	RW	30	0x3ffb003f	0000000000
EMMC_RESP0	0x7e300010	RW	32	0xffffffff	0000000000
EMMC_RESP1	0x7e300014	RW	32	0xffffffff	0000000000
EMMC_RESP2	0x7e300018	RW	32	0xffffffff	0000000000
EMMC_RESP3	0x7e30001c	RW	32	0xffffffff	0000000000
EMMC_DATA	0x7e300020	RW	32	0xffffffff	0000000000
EMMC_STATUS	0x7e300024	RW	29	0x1fff0f0f	0x1ff00000
EMMC_CONTROL0	0x7e300028	RW	27	0x07ff1fff	0000000000
EMMC_CONTROL1	0x7e30002c	RW	27	0x070fffe7	0000000000
EMMC_INTERRUPT	0x7e300030	RW	32	0xffffffff	0000000000
EMMC_IRPT_MASK	0x7e300034	RW	32	0xffffffff	0000000000
EMMC_IRPT_EN	0x7e300038	RW	32	0xffffffff	0000000000
EMMC_CONTROL2	0x7e30003c	RW	32	0xc0ff009f	0x00080000
EMMC_HWCAP0	0x7e300040	RW	32	0xffffffff	0000000000
EMMC_HWCAP1	0x7e300044	RW	26	0x03ffef77	0x03000777
EMMC_HWMAXAMP0	0x7e300048	RW	24	0x00ffffff	0000000000
EMMC_FORCE_IRPT	0x7e300050	RW	32	0xffff00ff	0x00000001
EMMC_DMA_STATUS	0x7e300054	RW	32	0xffff00ff	0000000000
EMMC_BOOT_TIMEOUT	0x7e300070	RW	32	0xffffffff	0000000000
EMMC_DBG_SEL	0x7e300074	RW	1	0x00000001	0000000000
EMMC_EXRDFIFO_CFG	0x7e300080	RW	3	0x00000007	0000000000
EMMC_EXRDFIFO_EN	0x7e300084	RW	1	0x00000001	0000000000
EMMC_TUNE_STEP	0x7e300088	RW	3	0x00000007	0000000000
EMMC_TUNE_STEPS_STD	0x7e30008c	RW	6	0x0000003f	0000000000
EMMC_TUNE_STEPS_DDR	0x7e300090	RW	6	0x0000003f	0000000000
EMMC_BUS_CTRL	0x7e3000e0	RW	32	0xffffffff	0000000000
EMMC_SPI_INT_SPT	0x7e3000f0	RW	8	0x000000ff	0000000000
EMMC_SLOTISR_VER	0x7e3000fc	RW	32	0xffff00ff	0x99020000

Register:EMMC_BLKSIZECNT (0x7e300004)

field_name	start_bit	end_bit	set	clear	reset
EMMC_BLKSIZECNT_BLKSIZE	0	11	0x00000fff	0xfffff000	0x0
EMMC_BLKSIZECNT_SDMA_BLKSIZE	12	14	0x00007000	0xffff8fff	0x0
EMMC_BLKSIZECNT_BLKSIZE_MS1	15	15	0x00008000	0xffff7fff	0x0
EMMC_BLKSIZECNT_BLKCNT	16	31	0xffff0000	0x0000ffff	0x0

Register:EMMC_CMDTM (0x7e30000c)

field_name	start_bit	end_bit	set	clear	reset
EMMC_CMDTM_TM_DMA_EN	0	0	0x00000001	0xfffffffe	0x0
EMMC_CMDTM_TM_BLKCNT_EN	1	1	0x00000002	0xfffffffd	0x0
EMMC_CMDTM_TM_AUTO_CMD_EN	2	3	0x0000000c	0xfffffff3	0x0
EMMC_CMDTM_TM_DAT_DIR	4	4	0x00000010	0xffffffef	0x0
EMMC_CMDTM_TM_MULTI_BLOCK	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	15	NA	NA	NA
EMMC_CMDTM_CMD_RSPNS_TYPE	16	17	0x00030000	0xfffcffff	0x0
missing definiton	18	18	NA	NA	NA
EMMC_CMDTM_CMD_CRCCHK_EN	19	19	0x00080000	0xfff7ffff	0x0
EMMC_CMDTM_CMD_IXCHK_EN	20	20	0x00100000	0xffefffff	0x0
EMMC_CMDTM_CMD_ISDATA	21	21	0x00200000	0xffdfffff	0x0
EMMC_CMDTM_CMD_TYPE	22	23	0x00c00000	0xff3fffff	0x0
EMMC_CMDTM_CMD_INDEX	24	29	0x3f000000	0xc0ffffff	0x0

Register:EMMC_STATUS (0x7e300024)

field_name	start_bit	end_bit	set	clear	reset
EMMC_STATUS_CMD_INHIBIT	0	0	0x00000001	0xfffffffe	0x0
EMMC_STATUS_DAT_INHIBIT	1	1	0x00000002	0xfffffffd	0x0
EMMC_STATUS_DAT_ACTIVE	2	2	0x00000004	0xfffffffb	0x0
EMMC_STATUS_RETUNING_REQ	3	3	0x00000008	0xfffffff7	0x0
missing definiton	4	7	NA	NA	NA
EMMC_STATUS_WRITE_TRANSFER	8	8	0x00000100	0xfffffeff	0x0
EMMC_STATUS_READ_TRANSFER	9	9	0x00000200	0xfffffdff	0x0
EMMC_STATUS_NEW_WRITE_DATA	10	10	0x00000400	0xfffffbff	0x0
EMMC_STATUS_NEW_READ_DATA	11	11	0x00000800	0xfffff7ff	0x0
missing definiton	12	15	NA	NA	NA
EMMC_STATUS_CARD_INSERT	16	16	0x00010000	0xfffeffff	0x0
EMMC_STATUS_CARD_STABLE	17	17	0x00020000	0xfffdffff	0x0
EMMC_STATUS_CARD_DETECT	18	18	0x00040000	0xfffbffff	0x0
EMMC_STATUS_WRT_PROTECT	19	19	0x00080000	0xfff7ffff	0x0
EMMC_STATUS_DAT_LEVEL0	20	23	0x00f00000	0xff0fffff	0xf
EMMC_STATUS_CMD_LEVEL	24	24	0x01000000	0xfeffffff	0x1
EMMC_STATUS_DAT_LEVEL1	25	28	0x1e000000	0xe1ffffff	0xf

Register:EMMC_CONTROL0 (0x7e300028)

field_name	start_bit	end_bit	set	clear	reset
EMMC_CONTROL0_HCTL_LED	0	0	0x00000001	0xfffffffe	0x0
EMMC_CONTROL0_HCTL_DWIDTH	1	1	0x00000002	0xfffffffd	0x0
EMMC_CONTROL0_HCTL_HS_EN	2	2	0x00000004	0xfffffffb	0x0
EMMC_CONTROL0_HCTL_DMA	3	4	0x00000018	0xffffffe7	0x0
EMMC_CONTROL0_HCTL_8BIT	5	5	0x00000020	0xffffffdf	0x0
EMMC_CONTROL0_HCTL_CRDDET	6	6	0x00000040	0xffffffbf	0x0
EMMC_CONTROL0_HCTL_CRDDET_S	7	7	0x00000080	0xffffff7f	0x0
EMMC_CONTROL0_PWCTL_ON	8	8	0x00000100	0xfffffeff	0x0
EMMC_CONTROL0_PWCTL_SDVOLTS	9	11	0x00000e00	0xfffff1ff	0x0
EMMC_CONTROL0_PWCTL_HWRST	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
EMMC_CONTROL0_GAP_STOP	16	16	0x00010000	0xfffeffff	0x0
EMMC_CONTROL0_GAP_RESTART	17	17	0x00020000	0xfffdffff	0x0
EMMC_CONTROL0_READWAIT_EN	18	18	0x00040000	0xfffbffff	0x0
EMMC_CONTROL0_GAP_IEN	19	19	0x00080000	0xfff7ffff	0x0
EMMC_CONTROL0_SPI_MODE	20	20	0x00100000	0xffefffff	0x0
EMMC_CONTROL0_BOOT_EN	21	21	0x00200000	0xffdfffff	0x0
EMMC_CONTROL0_ALT_BOOT_EN	22	22	0x00400000	0xffbfffff	0x0
missing definiton	23	23	NA	NA	NA
EMMC_CONTROL0_WAKE_ONINT_EN	24	24	0x01000000	0xfeffffff	0x0
EMMC_CONTROL0_WAKE_ONINS_EN	25	25	0x02000000	0xfdffffff	0x0
EMMC_CONTROL0_WAKE_ONREM_EN	26	26	0x04000000	0xfbffffff	0x0

Register:EMMC_CONTROL1 (0x7e30002c)

field_name	start_bit	end_bit	set	clear	reset
EMMC_CONTROL1_CLK_INTLEN	0	0	0x00000001	0xfffffffe	0x0
EMMC_CONTROL1_CLK_STABLE	1	1	0x00000002	0xfffffffd	0x0
EMMC_CONTROL1_CLK_EN	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	4	NA	NA	NA
EMMC_CONTROL1_CLK_GENSEL	5	5	0x00000020	0xffffffdf	0x0
EMMC_CONTROL1_CLK_FREQ_MS2	6	7	0x000000c0	0xffffff3f	0x0
EMMC_CONTROL1_CLK_FREQ8	8	15	0x0000ff00	0xffff00ff	0x0
EMMC_CONTROL1_DATA_TOUNIT	16	19	0x000f0000	0xfff0ffff	0x0
missing definiton	20	23	NA	NA	NA
EMMC_CONTROL1_SRST_HC	24	24	0x01000000	0xfeffffff	0x0
EMMC_CONTROL1_SRST_CMD	25	25	0x02000000	0xfdffffff	0x0
EMMC_CONTROL1_SRST_DATA	26	26	0x04000000	0xfbffffff	0x0

Register:EMMC_INTERRUPT (0x7e300030)

field_name	start_bit	end_bit	set	clear	reset
EMMC_INTERRUPT_CMD_DONE	0	0	0x00000001	0xfffffffe	0x0
EMMC_INTERRUPT_DATA_DONE	1	1	0x00000002	0xfffffffd	0x0
EMMC_INTERRUPT_BLOCK_GAP	2	2	0x00000004	0xfffffffb	0x0
EMMC_INTERRUPT_DMA	3	3	0x00000008	0xfffffff7	0x0
EMMC_INTERRUPT_WRITE_RDY	4	4	0x00000010	0xffffffef	0x0
EMMC_INTERRUPT_READ_RDY	5	5	0x00000020	0xffffffdf	0x0
EMMC_INTERRUPT_CARD_IN	6	6	0x00000040	0xffffffbf	0x0
EMMC_INTERRUPT_CARD_OUT	7	7	0x00000080	0xffffff7f	0x0
EMMC_INTERRUPT_CARD	8	8	0x00000100	0xfffffeff	0x0
EMMC_INTERRUPT_INT_A	9	9	0x00000200	0xfffffdff	0x0
EMMC_INTERRUPT_INT_B	10	10	0x00000400	0xfffffbff	0x0
EMMC_INTERRUPT_INT_C	11	11	0x00000800	0xfffff7ff	0x0
EMMC_INTERRUPT_RETUNE	12	12	0x00001000	0xffffefff	0x0
EMMC_INTERRUPT_BOOTACK	13	13	0x00002000	0xffffdfff	0x0
EMMC_INTERRUPT_ENDBOOT	14	14	0x00004000	0xffffbfff	0x0
EMMC_INTERRUPT_ERR	15	15	0x00008000	0xffff7fff	0x0
EMMC_INTERRUPT_CTO_ERR	16	16	0x00010000	0xfffeffff	0x0
EMMC_INTERRUPT_CCRC_ERR	17	17	0x00020000	0xfffdffff	0x0
EMMC_INTERRUPT_CEND_ERR	18	18	0x00040000	0xfffbffff	0x0
EMMC_INTERRUPT_CBAD_ERR	19	19	0x00080000	0xfff7ffff	0x0
EMMC_INTERRUPT_DTO_ERR	20	20	0x00100000	0xffefffff	0x0
EMMC_INTERRUPT_DCRC_ERR	21	21	0x00200000	0xffdfffff	0x0
EMMC_INTERRUPT_DEND_ERR	22	22	0x00400000	0xffbfffff	0x0
EMMC_INTERRUPT_SDOFF_ERR	23	23	0x00800000	0xff7fffff	0x0
EMMC_INTERRUPT_ACMD_ERR	24	24	0x01000000	0xfeffffff	0x0
EMMC_INTERRUPT_ADMA_ERR	25	25	0x02000000	0xfdffffff	0x0
EMMC_INTERRUPT_TUNE_ERR	26	26	0x04000000	0xfbffffff	0x0
missing definiton	27	27	NA	NA	NA
EMMC_INTERRUPT_DMA_ERR	28	28	0x10000000	0xefffffff	0x0
EMMC_INTERRUPT_ATA_ERR	29	29	0x20000000	0xdfffffff	0x0
EMMC_INTERRUPT_OEM_ERR	30	31	0xc0000000	0x3fffffff	0x0

Register:EMMC_IRPT_MASK (0x7e300034)

field_name	start_bit	end_bit	set	clear	reset
EMMC_IRPT_MASK_CMD_DONE	0	0	0x00000001	0xfffffffe	0x0
EMMC_IRPT_MASK_DATA_DONE	1	1	0x00000002	0xfffffffd	0x0
EMMC_IRPT_MASK_BLOCK_GAP	2	2	0x00000004	0xfffffffb	0x0
EMMC_IRPT_MASK_DMA	3	3	0x00000008	0xfffffff7	0x0
EMMC_IRPT_MASK_WRITE_RDY	4	4	0x00000010	0xffffffef	0x0
EMMC_IRPT_MASK_READ_RDY	5	5	0x00000020	0xffffffdf	0x0
EMMC_IRPT_MASK_CARD_IN	6	6	0x00000040	0xffffffbf	0x0
EMMC_IRPT_MASK_CARD_OUT	7	7	0x00000080	0xffffff7f	0x0
EMMC_IRPT_MASK_CARD	8	8	0x00000100	0xfffffeff	0x0
EMMC_IRPT_MASK_INT_A	9	9	0x00000200	0xfffffdff	0x0
EMMC_IRPT_MASK_INT_B	10	10	0x00000400	0xfffffbff	0x0
EMMC_IRPT_MASK_INT_C	11	11	0x00000800	0xfffff7ff	0x0
EMMC_IRPT_MASK_RETUNE	12	12	0x00001000	0xffffefff	0x0
EMMC_IRPT_MASK_BOOTACK	13	13	0x00002000	0xffffdfff	0x0
EMMC_IRPT_MASK_ENDBOOT	14	14	0x00004000	0xffffbfff	0x0
missing definiton	15	15	NA	NA	NA
EMMC_IRPT_MASK_CTO_ERR	16	16	0x00010000	0xfffeffff	0x0
EMMC_IRPT_MASK_CCRC_ERR	17	17	0x00020000	0xfffdffff	0x0
EMMC_IRPT_MASK_CEND_ERR	18	18	0x00040000	0xfffbffff	0x0
EMMC_IRPT_MASK_CBAD_ERR	19	19	0x00080000	0xfff7ffff	0x0
EMMC_IRPT_MASK_DTO_ERR	20	20	0x00100000	0xffefffff	0x0
EMMC_IRPT_MASK_DCRC_ERR	21	21	0x00200000	0xffdfffff	0x0
EMMC_IRPT_MASK_DEND_ERR	22	22	0x00400000	0xffbfffff	0x0
EMMC_IRPT_MASK_SDOFF_ERR	23	23	0x00800000	0xff7fffff	0x0
EMMC_IRPT_MASK_ACMD_ERR	24	24	0x01000000	0xfeffffff	0x0
EMMC_IRPT_MASK_ADMA_ERR	25	25	0x02000000	0xfdffffff	0x0
missing definiton	26	27	NA	NA	NA
EMMC_IRPT_MASK_DMA_ERR	28	28	0x10000000	0xefffffff	0x0
EMMC_IRPT_MASK_ATA_ERR	29	29	0x20000000	0xdfffffff	0x0
EMMC_IRPT_MASK_OEM_ERR	30	31	0xc0000000	0x3fffffff	0x0

Register:EMMC_IRPT_EN (0x7e300038)

field_name	start_bit	end_bit	set	clear	reset
EMMC_IRPT_EN_CMD_DONE	0	0	0x00000001	0xfffffffe	0x0
EMMC_IRPT_EN_DATA_DONE	1	1	0x00000002	0xfffffffd	0x0
EMMC_IRPT_EN_BLOCK_GAP	2	2	0x00000004	0xfffffffb	0x0
EMMC_IRPT_EN_DMA	3	3	0x00000008	0xfffffff7	0x0
EMMC_IRPT_EN_WRITE_RDY	4	4	0x00000010	0xffffffef	0x0
EMMC_IRPT_EN_READ_RDY	5	5	0x00000020	0xffffffdf	0x0
EMMC_IRPT_EN_CARD_IN	6	6	0x00000040	0xffffffbf	0x0
EMMC_IRPT_EN_CARD_OUT	7	7	0x00000080	0xffffff7f	0x0
EMMC_IRPT_EN_CARD	8	8	0x00000100	0xfffffeff	0x0
EMMC_IRPT_EN_INT_A	9	9	0x00000200	0xfffffdff	0x0
EMMC_IRPT_EN_INT_B	10	10	0x00000400	0xfffffbff	0x0
EMMC_IRPT_EN_INT_C	11	11	0x00000800	0xfffff7ff	0x0
EMMC_IRPT_EN_RETUNE	12	12	0x00001000	0xffffefff	0x0
EMMC_IRPT_EN_BOOTACK	13	13	0x00002000	0xffffdfff	0x0
EMMC_IRPT_EN_ENDBOOT	14	14	0x00004000	0xffffbfff	0x0
missing definiton	15	15	NA	NA	NA
EMMC_IRPT_EN_CTO_ERR	16	16	0x00010000	0xfffeffff	0x0
EMMC_IRPT_EN_CCRC_ERR	17	17	0x00020000	0xfffdffff	0x0
EMMC_IRPT_EN_CEND_ERR	18	18	0x00040000	0xfffbffff	0x0
EMMC_IRPT_EN_CBAD_ERR	19	19	0x00080000	0xfff7ffff	0x0
EMMC_IRPT_EN_DTO_ERR	20	20	0x00100000	0xffefffff	0x0
EMMC_IRPT_EN_DCRC_ERR	21	21	0x00200000	0xffdfffff	0x0
EMMC_IRPT_EN_DEND_ERR	22	22	0x00400000	0xffbfffff	0x0
EMMC_IRPT_EN_SDOFF_ERR	23	23	0x00800000	0xff7fffff	0x0
EMMC_IRPT_EN_ACMD_ERR	24	24	0x01000000	0xfeffffff	0x0
EMMC_IRPT_EN_ADMA_ERR	25	25	0x02000000	0xfdffffff	0x0
EMMC_IRPT_EN_TUNE_ERR	26	26	0x04000000	0xfbffffff	0x0
missing definiton	27	27	NA	NA	NA
EMMC_IRPT_EN_DMA_ERR	28	28	0x10000000	0xefffffff	0x0
EMMC_IRPT_EN_ATA_ERR	29	29	0x20000000	0xdfffffff	0x0
EMMC_IRPT_EN_OEM_ERR	30	31	0xc0000000	0x3fffffff	0x0

Register:EMMC_CONTROL2 (0x7e30003c)

field_name	start_bit	end_bit	set	clear	reset
EMMC_CONTROL2_ACNOX_ERR	0	0	0x00000001	0xfffffffe	0x0
EMMC_CONTROL2_ACTO_ERR	1	1	0x00000002	0xfffffffd	0x0
EMMC_CONTROL2_ACCRC_ERR	2	2	0x00000004	0xfffffffb	0x0
EMMC_CONTROL2_ACEND_ERR	3	3	0x00000008	0xfffffff7	0x0
EMMC_CONTROL2_ACBAD_ERR	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	6	NA	NA	NA
EMMC_CONTROL2_NOTC12_ERR	7	7	0x00000080	0xffffff7f	0x0
missing definiton	8	15	NA	NA	NA
EMMC_CONTROL2_UHSMODE	16	18	0x00070000	0xfff8ffff	0x0
EMMC_CONTROL2_SIGTYPE	19	19	0x00080000	0xfff7ffff	0x1
EMMC_CONTROL2_DRVTYPE	20	21	0x00300000	0xffcfffff	0x0
EMMC_CONTROL2_TUNEON	22	22	0x00400000	0xffbfffff	0x0
EMMC_CONTROL2_TUNED	23	23	0x00800000	0xff7fffff	0x0
missing definiton	24	29	NA	NA	NA
EMMC_CONTROL2_EN_AINT	30	30	0x40000000	0xbfffffff	0x0
EMMC_CONTROL2_EN_PSV	31	31	0x80000000	0x7fffffff	0x0

Register:EMMC_HWCAP0 (0x7e300040)

field_name	start_bit	end_bit	set	clear	reset
EMMC_HWCAP0_TCLKFREQ	0	5	0x0000003f	0xffffffc0	0x0
missing definiton	6	6	NA	NA	NA
EMMC_HWCAP0_TCLKUNIT	7	7	0x00000080	0xffffff7f	0x0
EMMC_HWCAP0_BASEMHZ	8	15	0x0000ff00	0xffff00ff	0x0
EMMC_HWCAP0_MAXLEN	16	17	0x00030000	0xfffcffff	0x0
EMMC_HWCAP0_XMEDBUS	18	18	0x00040000	0xfffbffff	0x0
EMMC_HWCAP0_ADMA2	19	19	0x00080000	0xfff7ffff	0x0
missing definiton	20	20	NA	NA	NA
EMMC_HWCAP0_HS	21	21	0x00200000	0xffdfffff	0x0
EMMC_HWCAP0_SDMA	22	22	0x00400000	0xffbfffff	0x0
EMMC_HWCAP0_RESUME	23	23	0x00800000	0xff7fffff	0x0
EMMC_HWCAP0_V3_3	24	24	0x01000000	0xfeffffff	0x0
EMMC_HWCAP0_V3_0	25	25	0x02000000	0xfdffffff	0x0
EMMC_HWCAP0_V1_8	26	26	0x04000000	0xfbffffff	0x0
missing definiton	27	27	NA	NA	NA
EMMC_HWCAP0_BUS64	28	28	0x10000000	0xefffffff	0x0
EMMC_HWCAP0_AINT	29	29	0x20000000	0xdfffffff	0x0
EMMC_HWCAP0_SLOT_TYPE	30	31	0xc0000000	0x3fffffff	0x0

Register:EMMC_HWCAP1 (0x7e300044)

field_name	start_bit	end_bit	set	clear	reset
EMMC_HWCAP1_SDR50	0	0	0x00000001	0xfffffffe	0x1
EMMC_HWCAP1_SDR104	1	1	0x00000002	0xfffffffd	0x1
EMMC_HWCAP1_DDR50	2	2	0x00000004	0xfffffffb	0x1
missing definiton	3	3	NA	NA	NA
EMMC_HWCAP1_DRV18_TYPEA	4	4	0x00000010	0xffffffef	0x1
EMMC_HWCAP1_DRV18_TYPEC	5	5	0x00000020	0xffffffdf	0x1
EMMC_HWCAP1_DRV18_TYPED	6	6	0x00000040	0xffffffbf	0x1
missing definiton	7	7	NA	NA	NA
EMMC_HWCAP1_RETUNE_TMR	8	11	0x00000f00	0xfffff0ff	0x7
missing definiton	12	12	NA	NA	NA
EMMC_HWCAP1_SDR50_TUNE	13	13	0x00002000	0xffffdfff	0x0
EMMC_HWCAP1_DATA_RETUNE	14	15	0x0000c000	0xffff3fff	0x0
EMMC_HWCAP1_MULTIPLIER	16	23	0x00ff0000	0xff00ffff	0x0
EMMC_HWCAP1_SPI_MODE	24	24	0x01000000	0xfeffffff	0x1
EMMC_HWCAP1_SPI_BLOCKMODE	25	25	0x02000000	0xfdffffff	0x1

Register:EMMC_HWMAXAMP0 (0x7e300048)

field_name	start_bit	end_bit	set	clear	reset
EMMC_HWMAXAMP0_AMP_33V	0	7	0x000000ff	0xffffff00	0x0
EMMC_HWMAXAMP0_AMP_30V	8	15	0x0000ff00	0xffff00ff	0x0
EMMC_HWMAXAMP0_AMP_18V	16	23	0x00ff0000	0xff00ffff	0x0

Register:EMMC_FORCE_IRPT (0x7e300050)

field_name	start_bit	end_bit	set	clear	reset
EMMC_FORCE_IRPT_CMD_DONE	0	0	0x00000001	0xfffffffe	0x1
EMMC_FORCE_IRPT_DATA_DONE	1	1	0x00000002	0xfffffffd	0x0
EMMC_FORCE_IRPT_BLOCK_GAP	2	2	0x00000004	0xfffffffb	0x0
EMMC_FORCE_IRPT_DMA	3	3	0x00000008	0xfffffff7	0x0
EMMC_FORCE_IRPT_WRITE_RDY	4	4	0x00000010	0xffffffef	0x0
EMMC_FORCE_IRPT_READ_RDY	5	5	0x00000020	0xffffffdf	0x0
EMMC_FORCE_IRPT_CARD_IN	6	6	0x00000040	0xffffffbf	0x0
EMMC_FORCE_IRPT_CARD_OUT	7	7	0x00000080	0xffffff7f	0x0
missing definiton	8	15	NA	NA	NA
EMMC_FORCE_IRPT_CTO_ERR	16	16	0x00010000	0xfffeffff	0x0
EMMC_FORCE_IRPT_CCRC_ERR	17	17	0x00020000	0xfffdffff	0x0
EMMC_FORCE_IRPT_CEND_ERR	18	18	0x00040000	0xfffbffff	0x0
EMMC_FORCE_IRPT_CBAD_ERR	19	19	0x00080000	0xfff7ffff	0x0
EMMC_FORCE_IRPT_DTO_ERR	20	20	0x00100000	0xffefffff	0x0
EMMC_FORCE_IRPT_DCRC_ERR	21	21	0x00200000	0xffdfffff	0x0
EMMC_FORCE_IRPT_DEND_ERR	22	22	0x00400000	0xffbfffff	0x0
EMMC_FORCE_IRPT_SDOFF_ERR	23	23	0x00800000	0xff7fffff	0x0
EMMC_FORCE_IRPT_ACMD_ERR	24	24	0x01000000	0xfeffffff	0x0
EMMC_FORCE_IRPT_ADMA_ERR	25	25	0x02000000	0xfdffffff	0x0
EMMC_FORCE_IRPT_TUNE_ERR	26	26	0x04000000	0xfbffffff	0x0
missing definiton	27	27	NA	NA	NA
EMMC_FORCE_IRPT_DMA_ERR	28	28	0x10000000	0xefffffff	0x0
EMMC_FORCE_IRPT_ATA_ERR	29	29	0x20000000	0xdfffffff	0x0
EMMC_FORCE_IRPT_OEM_ERR	30	31	0xc0000000	0x3fffffff	0x0

Register:EMMC_DMA_STATUS (0x7e300054)

field_name	start_bit	end_bit	set	clear	reset
EMMC_DMA_STATUS_ERR_AT	0	1	0x00000003	0xfffffffc	0x0
EMMC_DMA_STATUS_LEN_NOMATCH	2	2	0x00000004	0xfffffffb	0x0

Register:EMMC_BOOT_TIMEOUT (0x7e300070)

field_name	start_bit	end_bit	set	clear	reset
EMMC_BOOT_TIMEOUT_TIMEOUT	0	31	0xffffffff	0x00000000	0x0

Register:EMMC_DBG_SEL (0x7e300074)

field_name	start_bit	end_bit	set	clear	reset
EMMC_DBG_SEL_SELECT	0	0	0x00000001	0xfffffffe	0x0

Register:EMMC_EXRDFIFO_CFG (0x7e300080)

field_name	start_bit	end_bit	set	clear	reset
EMMC_EXRDFIFO_CFG_RD_THRSH	0	2	0x00000007	0xfffffff8	0x0

Register:EMMC_EXRDFIFO_EN (0x7e300084)

field_name	start_bit	end_bit	set	clear	reset
EMMC_EXRDFIFO_EN_ENABLE	0	0	0x00000001	0xfffffffe	0x0

Register:EMMC_TUNE_STEP (0x7e300088)

field_name	start_bit	end_bit	set	clear	reset
EMMC_TUNE_STEP_DELAY	0	2	0x00000007	0xfffffff8	0x0

Register:EMMC_TUNE_STEPS_STD (0x7e30008c)

field_name	start_bit	end_bit	set	clear	reset
EMMC_TUNE_STEPS_STD_STEPS	0	5	0x0000003f	0xffffffc0	0x0

Register:EMMC_TUNE_STEPS_DDR (0x7e300090)

field_name	start_bit	end_bit	set	clear	reset
EMMC_TUNE_STEPS_DDR_STEPS	0	5	0x0000003f	0xffffffc0	0x0

Register:EMMC_BUS_CTRL (0x7e3000e0)

field_name	start_bit	end_bit	set	clear	reset
EMMC_BUS_CTRL_CLK_PINS	0	2	0x00000007	0xfffffff8	0x0
EMMC_BUS_CTRL_IRQ_PINS	3	5	0x00000038	0xffffffc7	0x0
missing definiton	6	7	NA	NA	NA
EMMC_BUS_CTRL_BUS_WIDTH	8	14	0x00007f00	0xffff80ff	0x0
missing definiton	15	19	NA	NA	NA
EMMC_BUS_CTRL_IRQSEL	20	22	0x00700000	0xff8fffff	0x0
missing definiton	23	23	NA	NA	NA
EMMC_BUS_CTRL_BE_PWR	24	30	0x7f000000	0x80ffffff	0x0

Register:EMMC_SPI_INT_SPT (0x7e3000f0)

field_name	start_bit	end_bit	set	clear	reset
EMMC_SPI_INT_SPT_SELECT	0	7	0x000000ff	0xffffff00	0x0

Register:EMMC_SLOTISR_VER (0x7e3000fc)

field_name	start_bit	end_bit	set	clear	reset
EMMC_SLOTISR_VER_SLOT_STATUS	0	7	0x000000ff	0xffffff00	0x0
missing definiton	8	15	NA	NA	NA
EMMC_SLOTISR_VER_SDVERSION	16	23	0x00ff0000	0xff00ffff	0x2
EMMC_SLOTISR_VER_VENDOR	24	31	0xff000000	0x00ffffff	0x99

FPGA

Info

base	0x7e20b600
id	0x66706761

Registers

register name	address	type	width	mask
FPGA_VERSION	0x7e20b600	RO	32	0xffffffff
FPGA_SCRATCH	0x7e20b604	RW	32	0xffffffff
FPGA_CTRL0	0x7e20b608	RW	36	0xfffff3fff
FPGA_STATUS0	0x7e20b60c	RO	32	0xfff800ff
FPGA_DCM_WR_DATA	0x7e20b610	RW	24	0x00ffffff
FPGA_DCM_CTRL	0x7e20b614	RW	32	0xff0fffff
FPGA_DCM_RD_DATA	0x7e20b618	RO	16	0x0000ffff
FPGA_MB_XSYS_BUILD_NUM	0x7e20b700	RO	32	0xffffffff
FPGA_MB_XC0_BUILD_NUM	0x7e20b704	RO	32	0xffffffff
FPGA_MB_XC1_BUILD_NUM	0x7e20b708	RO	32	0xffffffff
FPGA_MB_XPERI_BUILD_NUM	0x7e20b70c	RO	32	0xffffffff
FPGA_MB_XH264_BUILD_NUM	0x7e20b710	RO	32	0xffffffff
FPGA_MB_XV3D_BUILD_NUM	0x7e20b714	RO	32	0xffffffff
FPGA_MB_XSLC1_BUILD_NUM	0x7e20b718	RO	32	0xffffffff
FPGA_MB_XSLC2_BUILD_NUM	0x7e20b71c	RO	32	0xffffffff
FPGA_MB_XSLC3_BUILD_NUM	0x7e20b720	RO	32	0xffffffff
FPGA_MB_CORE_CLK_FREQ	0x7e20b724	RO	32	0xffffffff
FPGA_MB_SDC_CLK_FREQ	0x7e20b728	RO	32	0xffffffff
FPGA_MB_SDC_H264_FREQ	0x7e20b72c	RO	32	0xffffffff
FPGA_MB_SDC_V3D_FREQ	0x7e20b730	RO	32	0xffffffff
FPGA_MB_SDC_ISP_FREQ	0x7e20b734	RO	32	0xffffffff

Unsupported defines

define	value
FPGA_A0_BASE	0x7e213000
FPGA_B0_BASE	0x7e214000
FPGA_CTRL0_OFFSET	0x08
FPGA_MB_BASE	0x7e20b700
FPGA_STATUS0_OFFSET	0x0C

Register:FPGA_CTRL0 (0x7e20b608)

field_name	start_bit	end_bit	set	clear	reset
FPGA_CTRL0_DIS_CTL0	0	0	0x00000001	0xfffffffe
FPGA_CTRL0_CAM_CTL0	0	0	0x00000001	0xfffffffe
missing definiton	1	-1	NA	NA	NA
FPGA_CTRL0_CAM_CTL1	1	1	0x00000002	0xfffffffd
FPGA_CTRL0_DIS_BL	1	1	0x00000002	0xfffffffd
missing definiton	2	0	NA	NA	NA
FPGA_CTRL0_CAM_CTL2	2	2	0x00000004	0xfffffffb
FPGA_CTRL0_DIS_CTL2	2	2	0x00000004	0xfffffffb
missing definiton	3	1	NA	NA	NA
FPGA_CTRL0_DIS_RST	3	3	0x00000008	0xfffffff7
FPGA_CTRL0_SD_PSU_EN	4	4	0x00000010	0xffffffef
FPGA_CTRL0_DIS_SW_SPI	5	5	0x00000020	0xffffffdf
FPGA_CTRL0_SW_SPI_SCL	6	6	0x00000040	0xffffffbf
FPGA_CTRL0_SW_SPI_SDA_O	7	7	0x00000080	0xffffff7f
FPGA_CTRL0_SW_SPI_CS	8	8	0x00000100	0xfffffeff
FPGA_CTRL0_SPI0_SEL_A	9	9	0x00000200	0xfffffdff
FPGA_CTRL0_SPI1_SEL	10	10	0x00000400	0xfffffbff
FPGA_CTRL0_DISP_BUFFER	11	11	0x00000800	0xfffff7ff
FPGA_CTRL0_SPI0_SEL_B	12	12	0x00001000	0xffffefff
FPGA_CTRL0_TV_ACTIVITY	13	13	0x00002000	0xffffdfff
missing definiton	14	15	NA	NA	NA
FPGA_CTRL0_TERMEN_DO	16	16	0x00010000	0xfffeffff
FPGA_CTRL0_TERMEN_CLK	17	17	0x00020000	0xfffdffff
FPGA_CTRL0_LV_SPARE_OUT	18	19	0x000c0000	0xfff3ffff
FPGA_CTRL0_SPARE_OUT	20	31	0xfff00000	0x000fffff

Register:FPGA_STATUS0 (0x7e20b60c)

field_name	start_bit	end_bit	set	clear	reset
FPGA_STATUS0_HW_ID	0	3	0x0000000f	0xfffffff0
FPGA_STATUS0_SD_WP	4	4	0x00000010	0xffffffef
FPGA_STATUS0_SD_CD	5	5	0x00000020	0xffffffdf
FPGA_STATUS0_NAND_RNB	6	6	0x00000040	0xffffffbf
FPGA_STATUS0_SW_SPI_SPI_IN	7	7	0x00000080	0xffffff7f
missing definiton	8	18	NA	NA	NA
FPGA_STATUS0_SPARE_IN	19	31	0xfff80000	0x0007ffff

Register:FPGA_DCM_WR_DATA (0x7e20b610)

field_name	start_bit	end_bit	set	clear	reset
FPGA_DCM_WR_DATA_DATA	0	15	0x0000ffff	0xffff0000
FPGA_DCM_WR_DATA_ADDRESS	16	23	0x00ff0000	0xff00ffff

Register:FPGA_DCM_CTRL (0x7e20b614)

field_name	start_bit	end_bit	set	clear	reset
FPGA_DCM_CTRL_REMOTE_RST	0	4	0x0000001f	0xffffffe0
missing definiton	5	7	NA	NA	NA
FPGA_DCM_CTRL_REMOTE_EN	8	12	0x00001f00	0xffffe0ff
missing definiton	13	15	NA	NA	NA
FPGA_DCM_CTRL_PERI_RST	16	19	0x000f0000	0xfff0ffff
missing definiton	20	23	NA	NA	NA
FPGA_DCM_CTRL_PERI_EN	24	27	0x0f000000	0xf0ffffff
FPGA_DCM_CTRL_PERI_WR_EN	28	31	0xf0000000	0x0fffffff

Register:FPGA_DCM_RD_DATA (0x7e20b618)

field_name	start_bit	end_bit	set	clear	reset
FPGA_DCM_RD_DATA_DATA	0	15	0x0000ffff	0xffff0000

GP

Info

description	GPIO control
base	0x7e200000
id	0x6770696f

Registers

register name	address	type	width	mask	reset
GP_FSEL0	0x7e200000	RW	30	0x3fffffff	0000000000
GP_FSEL1	0x7e200004	RW	30	0x3fffffff	0000000000
GP_FSEL2	0x7e200008	RW	30	0x3fffffff	0000000000
GP_FSEL3	0x7e20000c	RW	30	0x3fffffff	0000000000
GP_FSEL4	0x7e200010	RW	30	0x3fffffff	0000000000
GP_FSEL5	0x7e200014	RW	30	0x3fffffff	0000000000
GP_FSEL6	0x7e200018	RW	30	0x3fffffff	0000000000
GP_SET0	0x7e20001c	RW	32	0xffffffff	0000000000
GP_SET1	0x7e200020	RW	32	0xffffffff	0000000000
GP_SET2	0x7e200024	RW	6	0x0000003f	0000000000
GP_CLR0	0x7e200028	RW	32	0xffffffff	0000000000
GP_CLR1	0x7e20002c	RW	32	0xffffffff	0000000000
GP_CLR2	0x7e200030	RW	6	0x0000003f	0000000000
GP_LEV0	0x7e200034	RO	32	0xffffffff	0000000000
GP_LEV1	0x7e200038	RO	32	0xffffffff	0000000000
GP_LEV2	0x7e20003c	RO	6	0x0000003f	0000000000
GP_EDS0	0x7e200040	RW	32	0xffffffff	0000000000
GP_EDS1	0x7e200044	RW	32	0xffffffff	0000000000
GP_EDS2	0x7e200048	RW	6	0x0000003f	0000000000
GP_REN0	0x7e20004c	RW	32	0xffffffff	0000000000
GP_REN1	0x7e200050	RW	32	0xffffffff	0000000000
GP_REN2	0x7e200054	RW	6	0x0000003f	0000000000
GP_FEN0	0x7e200058	RW	32	0xffffffff	0000000000
GP_FEN1	0x7e20005c	RW	32	0xffffffff	0000000000
GP_FEN2	0x7e200060	RW	6	0x0000003f	0000000000
GP_HEN0	0x7e200064	RW	32	0xffffffff	0000000000
GP_HEN1	0x7e200068	RW	32	0xffffffff	0000000000
GP_HEN2	0x7e20006c	RW	6	0x0000003f	0000000000
GP_LEN0	0x7e200070	RW	32	0xffffffff	0000000000
GP_LEN1	0x7e200074	RW	32	0xffffffff	0000000000
GP_LEN2	0x7e200078	RW	6	0x0000003f	0000000000
GP_AREN0	0x7e20007c	RW	32	0xffffffff	0000000000
GP_AREN1	0x7e200080	RW	32	0xffffffff	0000000000
GP_AREN2	0x7e200084	RW	6	0x0000003f	0000000000
GP_AFEN0	0x7e200088	RW	32	0xffffffff	0000000000
GP_AFEN1	0x7e20008c	RW	32	0xffffffff	0000000000
GP_AFEN2	0x7e200090	RW	6	0x0000003f	0000000000
GP_PUD	0x7e200094	RW	2	0x00000003	0000000000
GP_PUDCLK0	0x7e200098	RW	32	0xffffffff	0000000000
GP_PUDCLK1	0x7e20009c	RW	32	0xffffffff	0000000000
GP_PUDCLK2	0x7e2000a0	RW	6	0x0000003f	0000000000
GP_SEN0	0x7e2000a4	RW	32	0xffffffff	0xffffffff
GP_SEN1	0x7e2000a8	RW	22	0x003fffff	0x003fffff
GP_GPTEST	0x7e2000b0	RW	4	0x0000000f	0000000000
GP_AJBCONF	0x7e2000c0	RW	32	0x80ffffff	0000000000
GP_AJBTMS	0x7e2000c4	RW	32	0xffffffff	0000000000
GP_AJBTDI	0x7e2000c8	RW	32	0xffffffff	0000000000
GP_AJBTDO	0x7e2000cc	RW	32	0xffffffff	0000000000

Register:GP_FSEL0 (0x7e200000)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL0_FSEL00	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL0_FSEL01	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL0_FSEL02	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL0_FSEL03	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL0_FSEL04	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL0_FSEL05	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL0_FSEL06	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL0_FSEL07	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL0_FSEL08	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL0_FSEL09	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL1 (0x7e200004)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL1_FSEL10	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL1_FSEL11	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL1_FSEL12	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL1_FSEL13	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL1_FSEL14	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL1_FSEL15	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL1_FSEL16	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL1_FSEL17	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL1_FSEL18	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL1_FSEL19	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL2 (0x7e200008)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL2_FSEL20	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL2_FSEL21	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL2_FSEL22	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL2_FSEL23	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL2_FSEL24	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL2_FSEL25	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL2_FSEL26	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL2_FSEL27	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL2_FSEL28	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL2_FSEL29	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL3 (0x7e20000c)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL3_FSEL30	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL3_FSEL31	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL3_FSEL32	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL3_FSEL33	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL3_FSEL34	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL3_FSEL35	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL3_FSEL36	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL3_FSEL37	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL3_FSEL38	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL3_FSEL39	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL4 (0x7e200010)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL4_FSEL40	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL4_FSEL41	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL4_FSEL42	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL4_FSEL43	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL4_FSEL44	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL4_FSEL45	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL4_FSEL46	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL4_FSEL47	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL4_FSEL48	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL4_FSEL49	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL5 (0x7e200014)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL5_FSEL50	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL5_FSEL51	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL5_FSEL52	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL5_FSEL53	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL5_FSEL54	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL5_FSEL55	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL5_FSEL56	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL5_FSEL57	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL5_FSEL58	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL5_FSEL59	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_FSEL6 (0x7e200018)

field_name	start_bit	end_bit	set	clear	reset
GP_FSEL6_FSEL60	0	2	0x00000007	0xfffffff8	0x0
GP_FSEL6_FSEL61	3	5	0x00000038	0xffffffc7	0x0
GP_FSEL6_FSEL62	6	8	0x000001c0	0xfffffe3f	0x0
GP_FSEL6_FSEL63	9	11	0x00000e00	0xfffff1ff	0x0
GP_FSEL6_FSEL64	12	14	0x00007000	0xffff8fff	0x0
GP_FSEL6_FSEL65	15	17	0x00038000	0xfffc7fff	0x0
GP_FSEL6_FSEL66	18	20	0x001c0000	0xffe3ffff	0x0
GP_FSEL6_FSEL67	21	23	0x00e00000	0xff1fffff	0x0
GP_FSEL6_FSEL68	24	26	0x07000000	0xf8ffffff	0x0
GP_FSEL6_FSEL69	27	29	0x38000000	0xc7ffffff	0x0

Register:GP_SET0 (0x7e20001c)

field_name	start_bit	end_bit	set	clear	reset
GP_SET0_SETn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_SET1 (0x7e200020)

field_name	start_bit	end_bit	set	clear	reset
GP_SET1_SETn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_SET2 (0x7e200024)

field_name	start_bit	end_bit	set	clear	reset
GP_SET2_SETn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_CLR0 (0x7e200028)

field_name	start_bit	end_bit	set	clear	reset
GP_CLR0_CLRn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_CLR1 (0x7e20002c)

field_name	start_bit	end_bit	set	clear	reset
GP_CLR1_CLRn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_CLR2 (0x7e200030)

field_name	start_bit	end_bit	set	clear	reset
GP_CLR2_CLRn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_LEV0 (0x7e200034)

field_name	start_bit	end_bit	set	clear	reset
GP_LEV0_LEVn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_LEV1 (0x7e200038)

field_name	start_bit	end_bit	set	clear	reset
GP_LEV1_LEVn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_LEV2 (0x7e20003c)

field_name	start_bit	end_bit	set	clear	reset
GP_LEV2_LEVn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_EDS0 (0x7e200040)

field_name	start_bit	end_bit	set	clear	reset
GP_EDS0_EDSn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_EDS1 (0x7e200044)

field_name	start_bit	end_bit	set	clear	reset
GP_EDS1_EDSn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_EDS2 (0x7e200048)

field_name	start_bit	end_bit	set	clear	reset
GP_EDS2_EDSn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_REN0 (0x7e20004c)

field_name	start_bit	end_bit	set	clear	reset
GP_REN0_RENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_REN1 (0x7e200050)

field_name	start_bit	end_bit	set	clear	reset
GP_REN1_RENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_REN2 (0x7e200054)

field_name	start_bit	end_bit	set	clear	reset
GP_REN2_RENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_FEN0 (0x7e200058)

field_name	start_bit	end_bit	set	clear	reset
GP_FEN0_FENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_FEN1 (0x7e20005c)

field_name	start_bit	end_bit	set	clear	reset
GP_FEN1_FENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_FEN2 (0x7e200060)

field_name	start_bit	end_bit	set	clear	reset
GP_FEN2_FENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_HEN0 (0x7e200064)

field_name	start_bit	end_bit	set	clear	reset
GP_HEN0_HENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_HEN1 (0x7e200068)

field_name	start_bit	end_bit	set	clear	reset
GP_HEN1_HENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_HEN2 (0x7e20006c)

field_name	start_bit	end_bit	set	clear	reset
GP_HEN2_HENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_LEN0 (0x7e200070)

field_name	start_bit	end_bit	set	clear	reset
GP_LEN0_LENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_LEN1 (0x7e200074)

field_name	start_bit	end_bit	set	clear	reset
GP_LEN1_LENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_LEN2 (0x7e200078)

field_name	start_bit	end_bit	set	clear	reset
GP_LEN2_LENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_AREN0 (0x7e20007c)

field_name	start_bit	end_bit	set	clear	reset
GP_AREN0_ARENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_AREN1 (0x7e200080)

field_name	start_bit	end_bit	set	clear	reset
GP_AREN1_ARENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_AREN2 (0x7e200084)

field_name	start_bit	end_bit	set	clear	reset
GP_AREN2_ARENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_AFEN0 (0x7e200088)

field_name	start_bit	end_bit	set	clear	reset
GP_AFEN0_AFENn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_AFEN1 (0x7e20008c)

field_name	start_bit	end_bit	set	clear	reset
GP_AFEN1_AFENn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_AFEN2 (0x7e200090)

field_name	start_bit	end_bit	set	clear	reset
GP_AFEN2_AFENn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_PUD (0x7e200094)

field_name	start_bit	end_bit	set	clear	reset
GP_PUD_PUD	0	1	0x00000003	0xfffffffc	0x0

Register:GP_PUDCLK0 (0x7e200098)

field_name	start_bit	end_bit	set	clear	reset
GP_PUDCLK0_PUDCLKn0	0	31	0xffffffff	0x00000000	0x0

Register:GP_PUDCLK1 (0x7e20009c)

field_name	start_bit	end_bit	set	clear	reset
GP_PUDCLK1_PUDCLKn32	0	31	0xffffffff	0x00000000	0x0

Register:GP_PUDCLK2 (0x7e2000a0)

field_name	start_bit	end_bit	set	clear	reset
GP_PUDCLK2_PUDCLKn64	0	5	0x0000003f	0xffffffc0	0x0

Register:GP_SEN0 (0x7e2000a4)

field_name	start_bit	end_bit	set	clear	reset
GP_SEN0_SEN	0	31	0xffffffff	0x00000000	0xffffffff

Register:GP_SEN1 (0x7e2000a8)

field_name	start_bit	end_bit	set	clear	reset
GP_SEN1_SEN	0	21	0x003fffff	0xffc00000	0x3fffff

Register:GP_GPTEST (0x7e2000b0)

field_name	start_bit	end_bit	set	clear	reset
GP_GPTEST_SMPS	0	0	0x00000001	0xfffffffe	0x0
GP_GPTEST_SPARE	1	3	0x0000000e	0xfffffff1	0x0

H264

Info

base	0x7f000000
id	0x68323634

Registers

register name	address	type	width	mask	reset
H264_RC	0x7f000000	RW	32	0xffffffff

HD

Info

base	0x7e808000
id	0x48444d49

Registers

register name	address	type	width	mask	reset
HD_HDM_CTL	0x7e80800c	RW	10	0x000003f7	0x000000f0
HD_MAI_CTL	0x7e808014	RW	16	0x0000ffff	0x00000020
HD_MAI_THR	0x7e808018	RW	32	0xffffffff	0x01010101
HD_MAI_FMT	0x7e80801c	RW	32	0xffffffff	0000000000
HD_MAI_DAT	0x7e808020	RW	32	0xffffffff	0000000000
HD_SPARE	0x7e808024	RW	32	0xffffffff	0000000000
HD_MAI_SMP	0x7e80802c	RW	32	0xffffffff	0000000000
HD_VID_CTL	0x7e808038	RW	32	0xfffc0000	0x00040000
HD_CSC_CTL	0x7e808040	RW	8	0x000000ff	0000000000
HD_CSC_12_11	0x7e808044	RW	32	0xffffffff	0000000000
HD_CSC_14_13	0x7e808048	RW	32	0xffffffff	0000000000
HD_CSC_22_21	0x7e80804c	RW	32	0xffffffff	0000000000
HD_CSC_24_23	0x7e808050	RW	32	0xffffffff	0000000000
HD_CSC_32_31	0x7e808054	RW	32	0xffffffff	0000000000
HD_CSC_34_33	0x7e808058	RW	32	0xffffffff	0000000000
HD_FRAME_CNT	0x7e808068	RW	32	0xffffffff	0000000000

Register:HD_HDM_CTL (0x7e80800c)

field_name	start_bit	end_bit	set	clear	reset
HD_HDM_CTL_ENABLE	0	0	0x00000001	0xfffffffe	0x0
HD_HDM_CTL_ENDIAN	1	1	0x00000002	0xfffffffd	0x0
HD_HDM_CTL_SW_RST	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
HD_HDM_CTL_PDSTBY	4	5	0x00000030	0xffffffcf	0x3
HD_HDM_CTL_RFSTBY	6	7	0x000000c0	0xffffff3f	0x3
HD_HDM_CTL_CECOVR	8	8	0x00000100	0xfffffeff	0x0
HD_HDM_CTL_CECRXD	9	9	0x00000200	0xfffffdff	0x0

Register:HD_MAI_CTL (0x7e808014)

field_name	start_bit	end_bit	set	clear	reset
HD_MAI_CTL_RST_MAI	0	0	0x00000001	0xfffffffe	0x0
HD_MAI_CTL_ERRORF	1	1	0x00000002	0xfffffffd	0x0
HD_MAI_CTL_ERRORE	2	2	0x00000004	0xfffffffb	0x0
HD_MAI_CTL_ENABLE	3	3	0x00000008	0xfffffff7	0x0
HD_MAI_CTL_CHNUM	4	7	0x000000f0	0xffffff0f	0x2
HD_MAI_CTL_PAREN	8	8	0x00000100	0xfffffeff	0x0
HD_MAI_CTL_FLUSH	9	9	0x00000200	0xfffffdff	0x0
HD_MAI_CTL_EMPTY	10	10	0x00000400	0xfffffbff	0x0
HD_MAI_CTL_FULL	11	11	0x00000800	0xfffff7ff	0x0
HD_MAI_CTL_WHOLSMP	12	12	0x00001000	0xffffefff	0x0
HD_MAI_CTL_CHALIGN	13	13	0x00002000	0xffffdfff	0x0
HD_MAI_CTL_BUSY	14	14	0x00004000	0xffffbfff	0x0
HD_MAI_CTL_DLATE	15	15	0x00008000	0xffff7fff	0x0

Register:HD_MAI_THR (0x7e808018)

field_name	start_bit	end_bit	set	clear	reset
HD_MAI_THR_DREQLOW	0	5	0x0000003f	0xffffffc0	0x1
missing definiton	6	7	NA	NA	NA
HD_MAI_THR_DREQHIGH	8	13	0x00003f00	0xffffc0ff	0x1
missing definiton	14	15	NA	NA	NA
HD_MAI_THR_PANICLOW	16	21	0x003f0000	0xffc0ffff	0x1
missing definiton	22	23	NA	NA	NA
HD_MAI_THR_PANICHIGH	24	29	0x3f000000	0xc0ffffff	0x1

Register:HD_VID_CTL (0x7e808038)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	17	NA	NA	NA
HD_VID_CTL_BLANKPIX	18	18	0x00040000	0xfffbffff	0x1
HD_VID_CTL_EMPRGB	19	19	0x00080000	0xfff7ffff	0x0
HD_VID_CTL_EMPSYNC	20	20	0x00100000	0xffefffff	0x0
HD_VID_CTL_FULRGB	21	21	0x00200000	0xffdfffff	0x0
HD_VID_CTL_FULSYNC	22	22	0x00400000	0xffbfffff	0x0
HD_VID_CTL_CLRRGB	23	23	0x00800000	0xff7fffff	0x0
HD_VID_CTL_CLRSYNC	24	24	0x01000000	0xfeffffff	0x0
HD_VID_CTL_ERROR	25	26	0x06000000	0xf9ffffff	0x0
HD_VID_CTL_HPOL	27	27	0x08000000	0xf7ffffff	0x0
HD_VID_CTL_VPOL	28	28	0x10000000	0xefffffff	0x0
HD_VID_CTL_RST_FRAMEC	29	29	0x20000000	0xdfffffff	0x0
HD_VID_CTL_UFEN	30	30	0x40000000	0xbfffffff	0x0
HD_VID_CTL_ENABLE	31	31	0x80000000	0x7fffffff	0x0

Register:HD_CSC_CTL (0x7e808040)

field_name	start_bit	end_bit	set	clear	reset
HD_CSC_CTL_ENABLE	0	0	0x00000001	0xfffffffe	0x0
HD_CSC_CTL_USERGB2YCC	1	1	0x00000002	0xfffffffd	0x0
HD_CSC_CTL_MODE	2	3	0x0000000c	0xfffffff3	0x0
HD_CSC_CTL_PADMSB	4	4	0x00000010	0xffffffef	0x0
HD_CSC_CTL_COLORD	5	7	0x000000e0	0xffffff1f	0x0

HDCP

Info

base	0x7e809000
id	0x48444350

Registers

register name	address	type	width	mask
HDCP_KEY_CTL	0x7e809000	RW	3	0x00000007
HDCP_KEY_ADR	0x7e809004	RW	8	0x000000ff
HDCP_KEY_KY0	0x7e809008	RW	32	0xffffffff
HDCP_KEY_KY1	0x7e80900c	RW	24	0x00ffffff

Register:HDCP_KEY_CTL (0x7e809000)

field_name	start_bit	end_bit	set	clear	reset
HDCP_KEY_CTL_START	0	0	0x00000001	0xfffffffe	0x0
HDCP_KEY_CTL_DONE	1	1	0x00000002	0xfffffffd	0x0
HDCP_KEY_CTL_DISHDCP	2	2	0x00000004	0xfffffffb	0x0

HDMI

Info

base	0x7e902000

Registers

register name	address	type	width	mask	reset
HDMI_PCI_MASK_CLEAR	(HDMI_BASE_ADDRESS + 0x340) + 0x2c	RW
HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL	(HDMI_BASE_ADDRESS + 0x2c0) + 0	RW
HDMI_PCI_MASK_STATUS	(HDMI_BASE_ADDRESS + 0x340) + 0x24	RW
HDMI_PCI_MASK_SET	(HDMI_BASE_ADDRESS + 0x340) + 0x28	RW
HDMI_HDMI_13_AUDIO_CFG_1	HDMI_BASE_ADDRESS + 336	RW
HDMI_TX_PHY_HDMI_TX_PHY_STATUS	(HDMI_BASE_ADDRESS + 0x2c0) + 24	RW
HDMI_TX_PHY_HDMI_TX_PHY_CTL_0	(HDMI_BASE_ADDRESS + 0x2c0) + 4	RW
HDMI_ASYNC_RM_PHASE_INC	(HDMI_BASE_ADDRESS + 0x300) + 12	RW
HDMI_HDMI_13_AUDIO_STATUS_1	HDMI_BASE_ADDRESS + 340	RW
HDMI_TX_PHY_HDMI_TX_PHY_SPARE	(HDMI_BASE_ADDRESS + 0x2c0) + 32	RW
HDMI_PCI_STATUS	(HDMI_BASE_ADDRESS + 0x340) + 0x18	RW
HDMI_ASYNC_RM_OFFSET	(HDMI_BASE_ADDRESS + 0x300) + 20	RW
HDMI_TX_PHY_HDMI_TX_PHY_CTL_2	(HDMI_BASE_ADDRESS + 0x2c0) + 12	RW
HDMI_HDMI_HBR_AUDIO_PACKET_HEADER	HDMI_BASE_ADDRESS + 344	RW
HDMI_ASYNC_RM_RATE_RATIO	(HDMI_BASE_ADDRESS + 0x300) + 4	RW
HDMI_RAM_PACKET_RSVD_1	(HDMI_BASE_ADDRESS + 0x400) + 508	RW
HDMI_PCI_SET	(HDMI_BASE_ADDRESS + 0x340) + 0x1c	RW
HDMI_ASYNC_RM_INTEGRATOR	(HDMI_BASE_ADDRESS + 0x300) + 16	RW
HDMI_PCI_CLEAR	(HDMI_BASE_ADDRESS + 0x340) + 0x20	RW
HDMI_ASYNC_RM_CONTROL	(HDMI_BASE_ADDRESS + 0x300) + 0	RW
HDMI_TX_PHY_HDMI65_TX_PHY_TMDS_CFG	(HDMI_BASE_ADDRESS + 0x2c0) + 20	RW
HDMI_PERT_INSERT_ERR_SEPARATION	HDMI_BASE_ADDRESS + 132	RW
HDMI_ASYNC_RM_FORMAT	(HDMI_BASE_ADDRESS + 0x300) + 24	RW
HDMI_ASYNC_RM_SAMPLE_INC	(HDMI_BASE_ADDRESS + 0x300) + 8	RW
HDMI_TX_PHY_HDMI_TX_PHY_CTL_1	(HDMI_BASE_ADDRESS + 0x2c0) + 8	RW
HDMI_RAM_PACKET_RSVD_0	(HDMI_BASE_ADDRESS + 0x400) + 504	RW
HDMI_TX_PHY_HDMI_TX_PHY_PLL_CFG	(HDMI_BASE_ADDRESS + 0x2c0) + 16	RW
HDMI_CORE_REV	0x7e902000	RW	16	0x0000ffff	0x00000600
HDMI_SW_RESET_CNTRL	0x7e902004	RW	2	0x00000003	0000000000
HDMI_HOTPLUG_INT	0x7e902008	RW	3	0x00000007	0x00000006
HDMI_HOTPLUG	0x7e90200c	RW	1	0x00000001	0000000000
HDMI_BKSV0	0x7e902010	RW	32	0xffffffff	0000000000
HDMI_BKSV1	0x7e902014	RW	32	0xffffffff	0000000000
HDMI_AN0	0x7e902018	RW	32	0xffffffff	0000000000
HDMI_AN1	0x7e90201c	RW	32	0xffffffff	0000000000
HDMI_AN_INFLUENCE_1	0x7e902020	RW	32	0xffffffff	0000000000
HDMI_AN_INFLUENCE_2	0x7e902024	RW	32	0xffffffff	0000000000
HDMI_TST_AN0	0x7e902028	RW	32	0xffffffff	0000000000
HDMI_TST_AN1	0x7e90202c	RW	32	0xffffffff	0000000000
HDMI_KSV_FIFO_0	0x7e902030	RW	32	0xffffffff	0000000000
HDMI_KSV_FIFO_1	0x7e902034	RW	8	0x000000ff	0000000000
HDMI_V	0x7e902038	RW	32	0xffffffff	0000000000
HDMI_HDCP_KEY_1	0x7e90203c	RW	32	0xffffff3f	0000000000
HDMI_HDCP_KEY_2	0x7e902040	RW	32	0xffffffff	0000000000
HDMI_HDCP_CTL	0x7e902044	RW	17	0x0001030f	0000000000
HDMI_CP_STATUS	0x7e902048	RW	32	0x8000031f	0x00000100
HDMI_CP_INTEGRITY	0x7e90204c	RW	32	0xffffff03	0000000000
HDMI_CP_INTEGRITY_CFG	0x7e902050	RW	17	0x0001ffff	0x00001000
HDMI_CP_CONFIG	0x7e902054	RW	31	0x7fffffff	0x00130080
HDMI_CP_TST	0x7e902058	RW	22	0x002001ff	0000000000
HDMI_FIFO_CTL	0x7e90205c	RW	16	0x0000efff	0000000000
HDMI_READ_POINTERS	0x7e902060	RW	31	0x7fffffff	0000000000
HDMI_ENCODER_CTL	0x7e902070	RW	1	0x00000001	0000000000
HDMI_PERT_CONFIG	0x7e902074	RW	12	0x00000fff	0000000000
HDMI_PERT_LFSR_PRELOAD	0x7e902078	RW	32	0xffffffff	0000000000
HDMI_PERT_LFSR_FEEDBACK_MASK	0x7e90207c	RW	32	0xffffffff	0000000000
HDMI_PERT_INSERT_ERR	0x7e902080	RW	24	0x00ffffff	0000000000
HDMI_PERT_INSERT_ERR_SEP	0x7e902084	RW	32	0xffffffff	0000000000
HDMI_PERT_TEST_LENGTH	0x7e902088	RW	32	0xffffffff	0000000000
HDMI_PERT_DATA	0x7e90208c	RW	24	0x00ffffff	0000000000
HDMI_MAI_CHANNEL_MAP	0x7e902090	RW	24	0x00ffffff	0x00fac688
HDMI_MAI_CONFIG	0x7e902094	RW	28	0x0fffffff	0x00000003
HDMI_MAI_FORMAT	0x7e902098	RW	32	0xffffffff	0000000000
HDMI_AUDIO_PACKET_CONFIG	0x7e90209c	RW	30	0x3fffffff	0x21000403
HDMI_RAM_PACKET_CONFIG	0x7e9020a0	RW	17	0x00013fff	0000000000
HDMI_RAM_PACKET_STATUS	0x7e9020a4	RW	14	0x00003fff	0000000000
HDMI_CRP_CFG	0x7e9020a8	RW	28	0x0fffffff	0x08000000
HDMI_CTS_0	0x7e9020ac	RW	20	0x000fffff	0000000000
HDMI_CTS_1	0x7e9020b0	RW	20	0x000fffff	0000000000
HDMI_CTS_PERIOD_0	0x7e9020b4	RW	32	0xff0fffff	0x010124f8
HDMI_CTS_PERIOD_1	0x7e9020b8	RW	32	0xff0fffff	0x010124f8
HDMI_BCH_CONFIGURATION	0x7e9020bc	RW	9	0x000001ff	0x00000083
HDMI_SCHEDULER_CONTROL	0x7e9020c0	RW	22	0x003fff7f	0x000cb008
HDMI_HORZA	0x7e9020c4	RW	15	0x00007fff	0x00000280
HDMI_HORZB	0x7e9020c8	RW	30	0x3fffffff	0x03018010
HDMI_VERTA0	0x7e9020cc	RW	25	0x01ffffff	0x002141e0
HDMI_VERTB0	0x7e9020d0	RW	22	0x003fffff	0x00000021
HDMI_VERTA1	0x7e9020d4	RW	25	0x01ffffff	0x002141e0
HDMI_VERTB1	0x7e9020d8	RW	22	0x003fffff	0x00000021
HDMI_TEST	0x7e9020dc	RW	12	0x00000fff	0000000000
HDMI_MBIST_TM	0x7e9020e0	RW	24	0x00ffffff	0000000000
HDMI_MISC_CONTROL	0x7e9020e4	RW	31	0x7fffffff	0000000000
HDMI_CEC_CNTRL_1	0x7e9020e8	RW	32	0xffffffff	0x0000e7be
HDMI_CEC_CNTRL_2	0x7e9020ec	RW	31	0x7fffffff	0x508d63d5
HDMI_CEC_CNTRL_3	0x7e9020f0	RW	32	0xffffffff	0x96826f5c
HDMI_CEC_CNTRL_4	0x7e9020f4	RW	32	0xffffffff	0xead4c3be
HDMI_CEC_CNTRL_5	0x7e9020f8	RW	28	0x0fffffff	0x004cfff5
HDMI_CEC_TX_DATA_1	0x7e9020fc	RW	32	0xffffffff	0000000000
HDMI_CEC_TX_DATA_2	0x7e902100	RW	32	0xffffffff	0000000000
HDMI_CEC_TX_DATA_3	0x7e902104	RW	32	0xffffffff	0000000000
HDMI_CEC_TX_DATA_4	0x7e902108	RW	32	0xffffffff	0000000000
HDMI_CEC_RX_DATA_1	0x7e90210c	RW	32	0xffffffff	0000000000
HDMI_CEC_RX_DATA_2	0x7e902110	RW	32	0xffffffff	0000000000
HDMI_CEC_RX_DATA_3	0x7e902114	RW	32	0xffffffff	0000000000
HDMI_CEC_RX_DATA_4	0x7e902118	RW	32	0xffffffff	0000000000
HDMI_PACKET_FIFO_CTL	0x7e90211c	RW	2	0x00000003	0000000000
HDMI_PACKET_FIFO_CFG	0x7e902120	RW	1	0x00000001	0000000000
HDMI_PACKET_FIFO_STATUS	0x7e902124	RW	26	0x03073f1f	0x03010000
HDMI_DVO_TIMING_ADJUST_A	0x7e902128	RW	20	0x000fffff	0x00088888
HDMI_DVO_TIMING_ADJUST_B	0x7e90212c	RW	32	0xffffffff	0x88888888
HDMI_DVO_TIMING_ADJUST_C	0x7e902130	RW	32	0xffffffff	0x88888888
HDMI_DVO_TIMING_ADJUST_D	0x7e902134	RW	32	0xffffffff	0x88888888
HDMI_DETECTED_HORZA	0x7e902138	RW	15	0x00007fff	0x00000280
HDMI_DETECTED_HORZB	0x7e90213c	RW	30	0x3ffffe00	0x03018010
HDMI_DETECTED_VERTA0	0x7e902140	RW	25	0x01ffffff	0x002141e0
HDMI_DETECTED_VERTB0	0x7e902144	RW	22	0x003fff00	0x00000021
HDMI_DETECTED_VERTA1	0x7e902148	RW	25	0x01ffffff	0x002141e0
HDMI_DETECTED_VERTB1	0x7e90214c	RW	22	0x003fff00	0x00000021
HDMI_13_AUDIO_CFG_1	0x7e902150	RW	10	0x000003ff	0x000000c8
HDMI_13_AUDIO_STATUS_1	0x7e902154	RW	1	0x00000001	0000000000
HDMI_HBR_AUDIO_PACKET_HEADER	0x7e902158	RW	20	0x000fffff	0x00000009
HDMI_POSTING_MASTER	0x7e90215c	RW	8	0x000000ff	0x000000ff
HDMI_TX_PHY_TX_PHY_RESET_CTL	0x7e9022c0	RW	32	0xffffffff	0x003f01ff
HDMI_TX_PHY_TX_PHY_CTL_0	0x7e9022c4	RW	32	0xffffffff	0x8e000000
HDMI_TX_PHY_TX_PHY_CTL_1	0x7e9022c8	RW	32	0xffffffff	0x0404a808
HDMI_TX_PHY_TX_PHY_CTL_2	0x7e9022cc	RW	32	0xffffffff	0x00a63004
HDMI_TX_PHY_TX_PHY_PLL_CFG	0x7e9022d0	RW	32	0xc3fbffff	0x07f80112
HDMI_TX_PHY_TX_PHY_TMDS_CFG	0x7e9022d4	RW	32	0xffffffff	0x0000001f
HDMI_TX_PHY_TX_PHY_STATUS	0x7e9022d8	RW	32	0xffffffff	0000000000
HDMI_TX_PHY_SPREAD_SPECTRUM	0x7e9022dc	RW	32	0xffffffff	0x00003c00
HDMI_TX_PHY_TX_PHY_SPARE	0x7e9022e0	RW	32	0xffffffff	0xffff0000
HDMI_CPU_STATUS	0x7e902340	RW	32	0xffffffff	0000000000
HDMI_CPU_SET	0x7e902344	RW	32	0xffffffff	0000000000
HDMI_CPU_CLEAR	0x7e902348	RW	32	0xffffffff	0000000000
HDMI_CPU_MASK_STATUS	0x7e90234c	RW	32	0xffffffff	0x0001ffff
HDMI_CPU_MASK_SET	0x7e902350	RW	32	0xffffffff	0x0001ffff
HDMI_CPU_MASK_CLEAR	0x7e902354	RW	32	0xffffffff	0x0001ffff
HDMI_RAM_GCP_0	0x7e902400	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_1	0x7e902404	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_2	0x7e902408	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_3	0x7e90240c	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_4	0x7e902410	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_5	0x7e902414	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_6	0x7e902418	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_7	0x7e90241c	RW	32	0xffffffff	0000000000
HDMI_RAM_GCP_8	0x7e902420	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_0	0x7e902424	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_1	0x7e902428	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_2	0x7e90242c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_3	0x7e902430	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_4	0x7e902434	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_5	0x7e902438	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_6	0x7e90243c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_7	0x7e902440	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_1_8	0x7e902444	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_0	0x7e902448	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_1	0x7e90244c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_2	0x7e902450	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_3	0x7e902454	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_4	0x7e902458	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_5	0x7e90245c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_6	0x7e902460	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_7	0x7e902464	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_2_8	0x7e902468	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_0	0x7e90246c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_1	0x7e902470	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_2	0x7e902474	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_3	0x7e902478	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_4	0x7e90247c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_5	0x7e902480	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_6	0x7e902484	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_7	0x7e902488	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_3_8	0x7e90248c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_0	0x7e902490	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_1	0x7e902494	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_2	0x7e902498	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_3	0x7e90249c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_4	0x7e9024a0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_5	0x7e9024a4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_6	0x7e9024a8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_7	0x7e9024ac	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_4_8	0x7e9024b0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_0	0x7e9024b4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_1	0x7e9024b8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_2	0x7e9024bc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_3	0x7e9024c0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_4	0x7e9024c4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_5	0x7e9024c8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_6	0x7e9024cc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_7	0x7e9024d0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_5_8	0x7e9024d4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_0	0x7e9024d8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_1	0x7e9024dc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_2	0x7e9024e0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_3	0x7e9024e4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_4	0x7e9024e8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_5	0x7e9024ec	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_6	0x7e9024f0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_7	0x7e9024f4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_6_8	0x7e9024f8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_0	0x7e9024fc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_1	0x7e902500	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_2	0x7e902504	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_3	0x7e902508	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_4	0x7e90250c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_5	0x7e902510	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_6	0x7e902514	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_7	0x7e902518	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_7_8	0x7e90251c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_0	0x7e902520	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_1	0x7e902524	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_2	0x7e902528	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_3	0x7e90252c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_4	0x7e902530	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_5	0x7e902534	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_6	0x7e902538	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_7	0x7e90253c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_8_8	0x7e902540	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_0	0x7e902544	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_1	0x7e902548	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_2	0x7e90254c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_3	0x7e902550	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_4	0x7e902554	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_5	0x7e902558	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_6	0x7e90255c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_7	0x7e902560	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_9_8	0x7e902564	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_0	0x7e902568	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_1	0x7e90256c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_2	0x7e902570	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_3	0x7e902574	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_4	0x7e902578	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_5	0x7e90257c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_6	0x7e902580	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_7	0x7e902584	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_10_8	0x7e902588	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_0	0x7e90258c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_1	0x7e902590	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_2	0x7e902594	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_3	0x7e902598	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_4	0x7e90259c	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_5	0x7e9025a0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_6	0x7e9025a4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_7	0x7e9025a8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_11_8	0x7e9025ac	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_0	0x7e9025b0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_1	0x7e9025b4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_2	0x7e9025b8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_3	0x7e9025bc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_4	0x7e9025c0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_5	0x7e9025c4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_6	0x7e9025c8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_7	0x7e9025cc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_12_8	0x7e9025d0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_0	0x7e9025d4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_1	0x7e9025d8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_2	0x7e9025dc	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_3	0x7e9025e0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_4	0x7e9025e4	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_5	0x7e9025e8	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_6	0x7e9025ec	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_7	0x7e9025f0	RW	32	0xffffffff	0000000000
HDMI_RAM_PACKET_13_8	0x7e9025f4	RW	32	0xffffffff	0000000000

Unsupported defines

define	value
HDMI_ASYNC_RM_BASE	(HDMI_BASE_ADDRESS + 0x300)
HDMI_DMA	0x110000
HDMI_INTR2_BASE	(HDMI_BASE_ADDRESS + 0x340)
HDMI_RAM_BASE	(HDMI_BASE_ADDRESS + 0x400)
HDMI_RBUS_REGS
HDMI_TX_PHY_BASE	(HDMI_BASE_ADDRESS + 0x2c0)

Register:HDMI_FIFO_CTL (0x7e90205c)

field_name	start_bit	end_bit	set	clear	reset
HDMI_FIFO_CTL_MASTER_SLAVE_N	0	0	0x00000001	0xfffffffe	0x0
HDMI_FIFO_CTL_USE_FULL	1	1	0x00000002	0xfffffffd	0x0
HDMI_FIFO_CTL_CAPTURE_POINTER	2	2	0x00000004	0xfffffffb	0x0
HDMI_FIFO_CTL_INV_CLK_XFR	3	3	0x00000008	0xfffffff7	0x0
HDMI_FIFO_CTL_USE_PLL_LOCK	4	4	0x00000010	0xffffffef	0x0
HDMI_FIFO_CTL_FIFO_RESET	5	5	0x00000020	0xffffffdf	0x0
HDMI_FIFO_CTL_RECENTER	6	6	0x00000040	0xffffffbf	0x0
HDMI_FIFO_CTL_ON_VB	7	7	0x00000080	0xffffff7f	0x0
HDMI_FIFO_CTL_VB_CNT	8	11	0x00000f00	0xfffff0ff	0x0
missing definiton	12	12	NA	NA	NA
HDMI_FIFO_CTL_USE_EMPTY	13	13	0x00002000	0xffffdfff	0x0
HDMI_FIFO_CTL_RECENTER_DONE	14	14	0x00004000	0xffffbfff	0x0
HDMI_FIFO_CTL_ON_VB_DONE	15	15	0x00008000	0xffff7fff	0x0

Register:HDMI_READ_POINTERS (0x7e902060)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	6	NA	NA	NA
HDMI_READ_POINTERS_DRFT_RD_ADDR	7	7	0x00000080	0xffffff7f	0x0
HDMI_READ_POINTERS_DRFT_WR_ADDR	8	15	0x0000ff00	0xffff00ff	0x0
HDMI_READ_POINTERS_DRFT_UNDERFLOW	16	16	0x00010000	0xfffeffff	0x0
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS	17	17	0x00020000	0xfffdffff	0x0
HDMI_READ_POINTERS_DRFT_ALMOST_MT	18	18	0x00040000	0xfffbffff	0x0
HDMI_READ_POINTERS_DRFT_OVERFLOW	19	19	0x00080000	0xfff7ffff	0x0
HDMI_READ_POINTERS_DRFT_FULL_MINUS	20	20	0x00100000	0xffefffff	0x0
HDMI_READ_POINTERS_DRFT_ALMOST_FULL	21	21	0x00200000	0xffdfffff	0x0
HDMI_READ_POINTERS_DRFT_HOLD_RD	22	22	0x00400000	0xffbfffff	0x0
HDMI_READ_POINTERS_DRFT_HOLD_WR	23	23	0x00800000	0xff7fffff	0x0
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD	24	26	0x07000000	0xf8ffffff	0x0
HDMI_READ_POINTERS_DOMAIN_WR_ADDR	27	29	0x38000000	0xc7ffffff	0x0
HDMI_READ_POINTERS_DOMAIN_HALF_FULL	30	30	0x40000000	0xbfffffff	0x0

Register:HDMI_SCHEDULER_CONTROL (0x7e9020c0)

field_name	start_bit	end_bit	set	clear	reset
HDMI_SCHEDULER_CONTROL_MODE_REQ	0	0	0x00000001	0xfffffffe	0x0
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE	1	1	0x00000002	0xfffffffd	0x0
HDMI_SCHEDULER_CONTROL_USE_PREDICTS	2	2	0x00000004	0xfffffffb	0x0
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT	3	3	0x00000008	0xfffffff7	0x1
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT	4	4	0x00000010	0xffffffef	0x0
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS	5	5	0x00000020	0xffffffdf	0x0
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID	8	13	0x00003f00	0xffffc0ff	0x30
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID	14	14	0x00004000	0xffffbfff	0x0
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT	15	15	0x00008000	0xffff7fff	0x1
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN	16	16	0x00010000	0xfffeffff	0x0
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN	17	17	0x00020000	0xfffdffff	0x0
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL	18	21	0x003c0000	0xffc3ffff	0x3

Register:HDMI_HORZA (0x7e9020c4)

field_name	start_bit	end_bit	set	clear	reset
HDMI_HORZA_MANUAL_HAP	0	12	0x00001fff	0xffffe000	0x280
HDMI_HORZA_MANUAL_HPOL	13	13	0x00002000	0xffffdfff	0x0
HDMI_HORZA_MANUAL_VPOL	14	14	0x00004000	0xffffbfff	0x0

Register:HDMI_HORZB (0x7e9020c8)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	8	NA	NA	NA
HDMI_HORZB_MANUAL_HFP	9	9	0x00000200	0xfffffdff	0x0
HDMI_HORZB_MANUAL_HSP	10	19	0x000ffc00	0xfff003ff	0x60
HDMI_HORZB_MANUAL_HBP	20	29	0x3ff00000	0xc00fffff	0x30

Register:HDMI_VERTA0 (0x7e9020cc)

field_name	start_bit	end_bit	set	clear	reset
HDMI_VERTA0_MANUAL_VAL0	0	12	0x00001fff	0xffffe000	0x1e0
HDMI_VERTA0_MANUAL_VFP0	13	19	0x000fe000	0xfff01fff	0xa
HDMI_VERTA0_MANUAL_VSP0	20	24	0x01f00000	0xfe0fffff	0x2

Register:HDMI_VERTB0 (0x7e9020d0)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	7	NA	NA	NA
HDMI_VERTB0_MANUAL_VBP0	8	8	0x00000100	0xfffffeff	0x0
HDMI_VERTB0_MANUAL_VSPO0	9	21	0x003ffe00	0xffc001ff	0x0

Register:HDMI_VERTA1 (0x7e9020d4)

field_name	start_bit	end_bit	set	clear	reset
HDMI_VERTA1_MANUAL_VAL1	0	12	0x00001fff	0xffffe000	0x1e0
HDMI_VERTA1_MANUAL_VFP1	13	19	0x000fe000	0xfff01fff	0xa
HDMI_VERTA1_MANUAL_VSP1	20	24	0x01f00000	0xfe0fffff	0x2

Register:HDMI_VERTB1 (0x7e9020d8)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	7	NA	NA	NA
HDMI_VERTB1_MANUAL_VBP1	8	8	0x00000100	0xfffffeff	0x0
HDMI_VERTB1_MANUAL_VSPO1	9	21	0x003ffe00	0xffc001ff	0x0

Register:HDMI_DETECTED_HORZA (0x7e902138)

field_name	start_bit	end_bit	set	clear	reset
HDMI_DETECTED_HORZA_MANUAL_HAP	0	12	0x00001fff	0xffffe000	0x280
HDMI_DETECTED_HORZA_MANUAL_HPOL	13	13	0x00002000	0xffffdfff	0x0
HDMI_DETECTED_HORZA_MANUAL_VPOL	14	14	0x00004000	0xffffbfff	0x0

Register:HDMI_DETECTED_HORZB (0x7e90213c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	8	NA	NA	NA
HDMI_DETECTED_HORZB_MANUAL_HFP	9	9	0x00000200	0xfffffdff	0x0
HDMI_DETECTED_HORZB_MANUAL_HSP	10	19	0x000ffc00	0xfff003ff	0x60
HDMI_DETECTED_HORZB_MANUAL_HBP	20	29	0x3ff00000	0xc00fffff	0x30

Register:HDMI_DETECTED_VERTA0 (0x7e902140)

field_name	start_bit	end_bit	set	clear	reset
HDMI_DETECTED_VERTA0_MANUAL_VAL0	0	12	0x00001fff	0xffffe000	0x1e0
HDMI_DETECTED_VERTA0_MANUAL_VFP0	13	19	0x000fe000	0xfff01fff	0xa
HDMI_DETECTED_VERTA0_MANUAL_VSP0	20	24	0x01f00000	0xfe0fffff	0x2

Register:HDMI_DETECTED_VERTB0 (0x7e902144)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	7	NA	NA	NA
HDMI_DETECTED_VERTB0_MANUAL_VBP0	8	8	0x00000100	0xfffffeff	0x0
HDMI_DETECTED_VERTB0_MANUAL_VSPO0	9	21	0x003ffe00	0xffc001ff	0x0

Register:HDMI_DETECTED_VERTA1 (0x7e902148)

field_name	start_bit	end_bit	set	clear	reset
HDMI_DETECTED_VERTA1_MANUAL_VAL1	0	12	0x00001fff	0xffffe000	0x1e0
HDMI_DETECTED_VERTA1_MANUAL_VFP1	13	19	0x000fe000	0xfff01fff	0xa
HDMI_DETECTED_VERTA1_MANUAL_VSP1	20	24	0x01f00000	0xfe0fffff	0x2

Register:HDMI_DETECTED_VERTB1 (0x7e90214c)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	7	NA	NA	NA
HDMI_DETECTED_VERTB1_MANUAL_VBP1	8	8	0x00000100	0xfffffeff	0x0
HDMI_DETECTED_VERTB1_MANUAL_VSPO1	9	21	0x003ffe00	0xffc001ff	0x0

I2C0

Info

base	0x7e205000

Registers

register name	address	type	width	mask	reset
I2C0_C	0x7e205000	RW	16	0x00008701	0000000000
I2C0_S	0x7e205004	RW	32	0xffffffff	0x00000050
I2C0_DLEN	0x7e205008	RW	16	0x0000ffff	0000000000
I2C0_A	0x7e20500c	RW	7	0x0000007f	0000000000
I2C0_FIFO	0x7e205010	RW	8	0x000000ff	0000000000
I2C0_DIV	0x7e205014	RW	16	0x0000ffff	0x000005dc
I2C0_DEL	0x7e205018	RW	32	0xffffffff	0x00300030
I2C0_CLKT	0x7e20501c	RW	16	0x0000ffff	0x00000040

I2C1

Info

base	0x7e804000

Registers

register name	address	type	width	mask	reset
I2C1_C	0x7e804000	RW	16	0x00008701	0000000000
I2C1_S	0x7e804004	RW	32	0xffffffff	0x00000050
I2C1_DLEN	0x7e804008	RW	16	0x0000ffff	0000000000
I2C1_A	0x7e80400c	RW	7	0x0000007f	0000000000
I2C1_FIFO	0x7e804010	RW	8	0x000000ff	0000000000
I2C1_DIV	0x7e804014	RW	16	0x0000ffff	0x000005dc
I2C1_DEL	0x7e804018	RW	32	0xffffffff	0x00300030
I2C1_CLKT	0x7e80401c	RW	16	0x0000ffff	0x00000040

I2C2

Info

base	0x7e805000

Registers

register name	address	type	width	mask	reset
I2C2_C	0x7e805000	RW	16	0x00008701	0000000000
I2C2_S	0x7e805004	RW	32	0xffffffff	0x00000050
I2C2_DLEN	0x7e805008	RW	16	0x0000ffff	0000000000
I2C2_A	0x7e80500c	RW	7	0x0000007f	0000000000
I2C2_FIFO	0x7e805010	RW	8	0x000000ff	0000000000
I2C2_DIV	0x7e805014	RW	16	0x0000ffff	0x000005dc
I2C2_DEL	0x7e805018	RW	32	0xffffffff	0x00300030
I2C2_CLKT	0x7e80501c	RW	16	0x0000ffff	0x00000040

I2C_SPI_SLV

Info

base	0x7e214000
id	0x73506783

Registers

register name	address	type	width	mask	reset
I2C_SPI_SLV_DR	0x7e214000	RW	32	0xffff3fff	0x00120000
I2C_SPI_SLV_RSR	0x7e214004	RW	6	0x0000003f	0000000000
I2C_SPI_SLV_SLV	0x7e214008	RW	7	0x0000007f	0000000000
I2C_SPI_SLV_CR	0x7e21400c	RW	17	0x0001ffff	0000000000
I2C_SPI_SLV_FR	0x7e214010	RW	16	0x0000ffff	0x00000012
I2C_SPI_SLV_IFLS	0x7e214014	RW	12	0x00000fff	0x00000492
I2C_SPI_SLV_IMSC	0x7e214018	RW	4	0x0000000f	0000000000
I2C_SPI_SLV_RIS	0x7e21401c	RW	4	0x0000000f	0x00000002
I2C_SPI_SLV_MIS	0x7e214020	RW	4	0x0000000f	0000000000
I2C_SPI_SLV_ICR	0x7e214024	RW	4	0x0000000f	0000000000
I2C_SPI_SLV_DMACR	0x7e214028	RW	3	0x00000007	0000000000
I2C_SPI_SLV_TDR	0x7e21402c	RW	8	0x000000ff	0000000000
I2C_SPI_SLV_VCSTAT	0x7e214030	RW	4	0x0000000f	0000000000
I2C_SPI_SLV_HCTRL	0x7e214034	RW	8	0x000000ff	0000000000
I2C_SPI_SLV_DEBUG1	0x7e214038	RW	26	0x03ffffff	0x0000000e
I2C_SPI_SLV_DEBUG2	0x7e21403c	RW	24	0x00ffffff	0x00400000

Register:I2C_SPI_SLV_DR (0x7e214000)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_DR_DATA	0	7	0x000000ff	0xffffff00	0x0
I2C_SPI_SLV_DR_OE	8	8	0x00000100	0xfffffeff	0x0
I2C_SPI_SLV_DR_UE	9	9	0x00000200	0xfffffdff	0x0
I2C_SPI_SLV_DR_TXDMAPREQ	10	10	0x00000400	0xfffffbff	0x0
I2C_SPI_SLV_DR_TXDMABREQ	11	11	0x00000800	0xfffff7ff	0x0
I2C_SPI_SLV_DR_RXDMAPREQ	12	12	0x00001000	0xffffefff	0x0
I2C_SPI_SLV_DR_RXDMABREQ	13	13	0x00002000	0xffffdfff	0x0
missing definiton	14	15	NA	NA	NA
I2C_SPI_SLV_DR_TXBUSY	16	16	0x00010000	0xfffeffff	0x0
I2C_SPI_SLV_DR_RXFE	17	17	0x00020000	0xfffdffff	0x1
I2C_SPI_SLV_DR_TXFF	18	18	0x00040000	0xfffbffff	0x0
I2C_SPI_SLV_DR_RXFF	19	19	0x00080000	0xfff7ffff	0x0
I2C_SPI_SLV_DR_TXFE	20	20	0x00100000	0xffefffff	0x1
I2C_SPI_SLV_DR_RXBUSY	21	21	0x00200000	0xffdfffff	0x0
I2C_SPI_SLV_DR_TXFLEVEL	22	26	0x07c00000	0xf83fffff	0x0
I2C_SPI_SLV_DR_RXFLEVEL	27	31	0xf8000000	0x07ffffff	0x0

Register:I2C_SPI_SLV_RSR (0x7e214004)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_RSR_OE	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_RSR_UE	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_RSR_TXDMAPREQ	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_RSR_TXDMABREQ	3	3	0x00000008	0xfffffff7	0x0
I2C_SPI_SLV_RSR_RXDMAPREQ	4	4	0x00000010	0xffffffef	0x0
I2C_SPI_SLV_RSR_RXDMABREQ	5	5	0x00000020	0xffffffdf	0x0

Register:I2C_SPI_SLV_SLV (0x7e214008)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_SLV_ADDR	0	6	0x0000007f	0xffffff80	0x0

Register:I2C_SPI_SLV_CR (0x7e21400c)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_CR_EN	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_CR_SPI	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_CR_I2C	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_CR_CPHA	3	3	0x00000008	0xfffffff7	0x0
I2C_SPI_SLV_CR_CPOL	4	4	0x00000010	0xffffffef	0x0
I2C_SPI_SLV_CR_ENSTAT	5	5	0x00000020	0xffffffdf	0x0
I2C_SPI_SLV_CR_ENCTRL	6	6	0x00000040	0xffffffbf	0x0
I2C_SPI_SLV_CR_BRK	7	7	0x00000080	0xffffff7f	0x0
I2C_SPI_SLV_CR_TXE	8	8	0x00000100	0xfffffeff	0x0
I2C_SPI_SLV_CR_RXE	9	9	0x00000200	0xfffffdff	0x0
I2C_SPI_SLV_CR_INV_RXF	10	10	0x00000400	0xfffffbff	0x0
I2C_SPI_SLV_CR_TESTFIFO	11	11	0x00000800	0xfffff7ff	0x0
I2C_SPI_SLV_CR_HOSTCTRLEN	12	12	0x00001000	0xffffefff	0x0
I2C_SPI_SLV_CR_INV_TXF	13	13	0x00002000	0xffffdfff	0x0

Register:I2C_SPI_SLV_FR (0x7e214010)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_FR_TXBUSY	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_FR_RXFE	1	1	0x00000002	0xfffffffd	0x1
I2C_SPI_SLV_FR_TXFF	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_FR_RXFF	3	3	0x00000008	0xfffffff7	0x0
I2C_SPI_SLV_FR_TXFE	4	4	0x00000010	0xffffffef	0x1
I2C_SPI_SLV_FR_RXBUSY	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	9	NA	NA	NA
missing definiton	7	10	NA	NA	NA
I2C_SPI_SLV_FR_TXFLEVEL	10	6	0x00000000000	0xffffffff111	0x0
I2C_SPI_SLV_FR_RXFLEVEL	11	15	0x0000f800	0xffff07ff	0x0

Register:I2C_SPI_SLV_IFLS (0x7e214014)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_IFLS_TXIFLSEL	0	2	0x00000007	0xfffffff8	0x2
I2C_SPI_SLV_IFLS_RXIFLSEL	3	5	0x00000038	0xffffffc7	0x2
I2C_SPI_SLV_IFLS_TXIFPSEL	6	8	0x000001c0	0xfffffe3f	0x2
I2C_SPI_SLV_IFLS_RXIFPSEL	9	11	0x00000e00	0xfffff1ff	0x2

Register:I2C_SPI_SLV_IMSC (0x7e214018)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_IMSC_RXIM	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_IMSC_TXIM	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_IMSC_BEIM	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_IMSC_OEIM	3	3	0x00000008	0xfffffff7	0x0

Register:I2C_SPI_SLV_RIS (0x7e21401c)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_RIS_RXRIS	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_RIS_TXRIS	1	1	0x00000002	0xfffffffd	0x1
I2C_SPI_SLV_RIS_BERIS	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_RIS_OERIS	3	3	0x00000008	0xfffffff7	0x0

Register:I2C_SPI_SLV_MIS (0x7e214020)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_MIS_RXMIS	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_MIS_TXMIS	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_MIS_BEMIS	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_MIS_OEMIS	3	3	0x00000008	0xfffffff7	0x0

Register:I2C_SPI_SLV_ICR (0x7e214024)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_ICR_RXIC	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_ICR_TXIC	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_ICR_BEIC	2	2	0x00000004	0xfffffffb	0x0
I2C_SPI_SLV_ICR_OEIC	3	3	0x00000008	0xfffffff7	0x0

Register:I2C_SPI_SLV_DMACR (0x7e214028)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_DMACR_RXDMAE	0	0	0x00000001	0xfffffffe	0x0
I2C_SPI_SLV_DMACR_TXDMAE	1	1	0x00000002	0xfffffffd	0x0
I2C_SPI_SLV_DMACR_DMAONERR	2	2	0x00000004	0xfffffffb	0x0

Register:I2C_SPI_SLV_TDR (0x7e21402c)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_TDR_DATA	0	7	0x000000ff	0xffffff00	0x0

Register:I2C_SPI_SLV_VCSTAT (0x7e214030)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_VCSTAT_DATA	0	3	0x0000000f	0xfffffff0	0x0

Register:I2C_SPI_SLV_HCTRL (0x7e214034)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_HCTRL_DATA	0	7	0x000000ff	0xffffff00	0x0

Register:I2C_SPI_SLV_DEBUG1 (0x7e214038)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_DEBUG1_DATA	0	25	0x03ffffff	0xfc000000	0xe

Register:I2C_SPI_SLV_DEBUG2 (0x7e21403c)

field_name	start_bit	end_bit	set	clear	reset
I2C_SPI_SLV_DEBUG2_DATA	0	23	0x00ffffff	0xff000000	0x400000

IC0

Info

base	0x7e002000
id	0x494e5445

Registers

register name	address	type	width	mask	reset
IC0_C	0x7e002000	RW	4	0x0000000f	0000000000
IC0_S	0x7e002004	RO	27	0x073f073f
IC0_SRC0	0x7e002008	RO	32	0xffffffff
IC0_SRC1	0x7e00200c	RO	32	0xffffffff
IC0_MASK0	0x7e002010	RW	31	0x77777777	0000000000
IC0_MASK1	0x7e002014	RW	31	0x77777777	0000000000
IC0_MASK2	0x7e002018	RW	31	0x77777777	0000000000
IC0_MASK3	0x7e00201c	RW	31	0x77777777	0000000000
IC0_MASK4	0x7e002020	RW	31	0x77777777	0000000000
IC0_MASK5	0x7e002024	RW	31	0x77777777	0000000000
IC0_MASK6	0x7e002028	RW	31	0x77777777	0000000000
IC0_MASK7	0x7e00202c	RW	31	0x77777777	0000000000
IC0_VADDR	0x7e002030	RW	32	0xfffffe00	0000000000
IC0_WAKEUP	0x7e002034	RW	32	0xfffffffe	0x10000000
IC0_PROFILE	0x7e002038	RW	16	0x0000ffff
IC0_FORCE0	0x7e002040	RW	32	0xffffffff	0000000000
IC0_FORCE1	0x7e002044	RW	32	0xffffffff	0000000000
IC0_FORCE0_SET	0x7e002048	RW	32	0xffffffff	0000000000
IC0_FORCE1_SET	0x7e00204c	RW	32	0xffffffff	0000000000
IC0_FORCE0_CLR	0x7e002050	RW	32	0xffffffff	0000000000
IC0_FORCE1_CLR	0x7e002054	RW	32	0xffffffff	0000000000

IC1

Info

base	0x7e002800
id	0x494e5445

Registers

register name	address	type	width	mask	reset
IC1_C	0x7e002800	RW	4	0x0000000f	0000000000
IC1_S	0x7e002804	RO	27	0x073f073f
IC1_SRC0	0x7e002808	RO	32	0xffffffff
IC1_SRC1	0x7e00280c	RO	32	0xffffffff
IC1_MASK0	0x7e002810	RW	31	0x77777777	0000000000
IC1_MASK1	0x7e002814	RW	31	0x77777777	0000000000
IC1_MASK2	0x7e002818	RW	31	0x77777777	0000000000
IC1_MASK3	0x7e00281c	RW	31	0x77777777	0000000000
IC1_MASK4	0x7e002820	RW	31	0x77777777	0000000000
IC1_MASK5	0x7e002824	RW	31	0x77777777	0000000000
IC1_MASK6	0x7e002828	RW	31	0x77777777	0000000000
IC1_MASK7	0x7e00282c	RW	31	0x77777777	0000000000
IC1_VADDR	0x7e002830	RW	32	0xfffffe00	0000000000
IC1_WAKEUP	0x7e002834	RW	32	0xfffffffe	0x10000000
IC1_PROFILE	0x7e002838	RW	16	0x0000ffff
IC1_FORCE0	0x7e002840	RW	32	0xffffffff	0000000000
IC1_FORCE1	0x7e002844	RW	32	0xffffffff	0000000000
IC1_FORCE0_SET	0x7e002848	RW	32	0xffffffff	0000000000
IC1_FORCE1_SET	0x7e00284c	RW	32	0xffffffff	0000000000
IC1_FORCE0_CLR	0x7e002850	RW	32	0xffffffff	0000000000
IC1_FORCE1_CLR	0x7e002854	RW	32	0xffffffff	0000000000

ISP

Info

base	0x7ea00000
id	0x20697370

Registers

register name	address	type	width	mask	reset
ISP_RC	0x7ea00000	RW	32	0xffffffff

JP

Info

base	0x7e005000
id	0x4a504547

Registers

register name	address	type
JP_CTRL	0x7e005000	RW
JP_ICST	0x7e005004	RW
JP_MCTRL	0x7e005008	RW
JP_DCCTRL	0x7e00500c	RW
JP_CBA	0x7e005010	RW
JP_NCB	0x7e005014	RW
JP_SDA	0x7e005018	RW
JP_NSB	0x7e00501c	RW
JP_SBO	0x7e005020	RW
JP_MOP	0x7e005024	RW
JP_HADDR	0x7e005028	RW
JP_HWDATA	0x7e00502c	RW
JP_MADDR	0x7e005030	RW
JP_MWDATA	0x7e005034	RW
JP_OADDR	0x7e005038	RW
JP_OWDATA	0x7e00503c	RW
JP_QADDR	0x7e005040	RW
JP_QWDATA	0x7e005044	RW
JP_QCTRL	0x7e005048	RW
JP_C0BA	0x7e00504c	RW
JP_C1BA	0x7e005050	RW
JP_C2BA	0x7e005054	RW
JP_C0S	0x7e005058	RW
JP_C1S	0x7e00505c	RW
JP_C2S	0x7e005060	RW
JP_C0W	0x7e005064	RW
JP_C1W	0x7e005068	RW
JP_C2W	0x7e00506c	RW

L1

Info

description	VC4-L1 control
base	0x7ee02000
id	0x4c314343

Registers

register name	address	type	width	mask	reset
L1_IC0_CONTROL	0x7ee02000	RW	7	0x0000007f	0000000000
L1_IC0_PRIORITY	0x7ee02004	RW	16	0x0000ffff	0x000034af
L1_IC0_FLUSH_S	0x7ee02008	RW	32	0xffffffe0	0000000000
L1_IC0_FLUSH_E	0x7ee0200c	RW	32	0xffffffe0	0xffffffff
L1_IC0_RD_HITS	0x7ee02040	RW	0	0000000000
L1_IC0_RD_MISSES	0x7ee02044	RO	0	0000000000
L1_IC0_BP_HITS	0x7ee02048	RO	0	0000000000
L1_IC0_BP_MISSES	0x7ee0204c	RO	0	0000000000
L1_IC0_RAS_PUSHES	0x7ee02050	RO	0	0000000000
L1_IC0_RAS_POPS	0x7ee02054	RO	0	0000000000
L1_IC0_RAS_UNDERFLOW	0x7ee02058	RO	0	0000000000
L1_IC1_CONTROL	0x7ee02080	RW	7	0x0000007f	0000000000
L1_IC1_PRIORITY	0x7ee02084	RW	16	0x0000ffff	0x000034af
L1_IC1_FLUSH_S	0x7ee02088	RW	32	0xffffffe0	0000000000
L1_IC1_FLUSH_E	0x7ee0208c	RW	32	0xffffffe0	0xffffffff
L1_IC1_RD_HITS	0x7ee020c0	RW	0	0000000000
L1_IC1_RD_MISSES	0x7ee020c4	RO	0	0000000000
L1_IC1_BP_HITS	0x7ee020c8	RO	0	0000000000
L1_IC1_BP_MISSES	0x7ee020cc	RO	0	0000000000
L1_IC1_RAS_PUSHES	0x7ee020d0	RO	0	0000000000
L1_IC1_RAS_POPS	0x7ee020d4	RO	0	0000000000
L1_IC1_RAS_UNDERFLOW	0x7ee020d8	RO	0	0000000000
L1_D_CONTROL	0x7ee02100	RW	4	0x0000000f	0000000000
L1_D_FLUSH_S	0x7ee02104	RW	30	0x3fffffe0	0000000000
L1_D_FLUSH_E	0x7ee02108	RW	30	0x3fffffe0	0x3fffffff
L1_D_PRIORITY	0x7ee0210c	RW	28	0x0fff0fff	0000000000
L1_D0_RD_HITS	0x7ee02140	RW	0	0000000000
L1_D0_RD_SNOOPS	0x7ee02144	RO	0	0000000000
L1_D0_RD_MISSES	0x7ee02148	RO	0	0000000000
L1_D0_RD_THRUS	0x7ee0214c	RO	0	0000000000
L1_D0_WR_HITS	0x7ee02150	RO	0	0000000000
L1_D0_WR_SNOOPS	0x7ee02154	RO	0	0000000000
L1_D0_WR_MISSES	0x7ee02158	RO	0	0000000000
L1_D0_WR_THRUS	0x7ee0215c	RO	0	0000000000
L1_D0_WBACKS	0x7ee02160	RO	0	0000000000
L1_D1_RD_HITS	0x7ee02180	RW	0	0000000000
L1_D1_RD_SNOOPS	0x7ee02184	RO	0	0000000000
L1_D1_RD_MISSES	0x7ee02188	RO	0	0000000000
L1_D1_RD_THRUS	0x7ee0218c	RO	0	0000000000
L1_D1_WR_HITS	0x7ee02190	RO	0	0000000000
L1_D1_WR_SNOOPS	0x7ee02194	RO	0	0000000000
L1_D1_WR_MISSES	0x7ee02198	RO	0	0000000000
L1_D1_WR_THRUS	0x7ee0219c	RO	0	0000000000
L1_D1_WBACKS	0x7ee021a0	RO	0	0000000000
L1_L1_SANDBOX_START0	0x7ee02800	RW	30	0x3fffffff	0x00000007
L1_L1_SANDBOX_END0	0x7ee02804	RW	30	0x3fffffe0	0x3fffffe0
L1_L1_SANDBOX_START1	0x7ee02808	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END1	0x7ee0280c	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START2	0x7ee02810	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END2	0x7ee02814	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START3	0x7ee02818	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END3	0x7ee0281c	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START4	0x7ee02820	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END4	0x7ee02824	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START5	0x7ee02828	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END5	0x7ee0282c	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START6	0x7ee02830	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END6	0x7ee02834	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_START7	0x7ee02838	RW	30	0x3fffffff	0000000000
L1_L1_SANDBOX_END7	0x7ee0283c	RW	30	0x3fffffe0	0000000000
L1_L1_SANDBOX_PERI_BR	0x7ee02840	RW	13	0x00001f1f	0x00000707

Register:L1_IC0_CONTROL (0x7ee02000)

field_name	start_bit	end_bit	set	clear	reset
L1_IC0_CONTROL_DISABLE	0	0	0x00000001	0xfffffffe	0x0
L1_IC0_CONTROL_START_FLUSH	1	1	0x00000002	0xfffffffd	0x0
L1_IC0_CONTROL_ENABLE_STATS	2	2	0x00000004	0xfffffffb	0x0
L1_IC0_CONTROL_BP_DISABLE	3	3	0x00000008	0xfffffff7	0x0
L1_IC0_CONTROL_RAS_DISABLE	4	4	0x00000010	0xffffffef	0x0
L1_IC0_CONTROL_DISABLE_VLINE	5	6	0x00000060	0xffffff9f	0x0

Register:L1_IC0_PRIORITY (0x7ee02004)

field_name	start_bit	end_bit	set	clear	reset
L1_IC0_PRIORITY_IC0_APRIORITY0	0	3	0x0000000f	0xfffffff0	0xf
L1_IC0_PRIORITY_IC0_APRIORITY1	4	7	0x000000f0	0xffffff0f	0xa
L1_IC0_PRIORITY_IC0_APRIORITY2	8	11	0x00000f00	0xfffff0ff	0x4
L1_IC0_PRIORITY_IC0_APRIORITY3	12	15	0x0000f000	0xffff0fff	0x3

Register:L1_IC1_CONTROL (0x7ee02080)

field_name	start_bit	end_bit	set	clear	reset
L1_IC1_CONTROL_DISABLE	0	0	0x00000001	0xfffffffe	0x0
L1_IC1_CONTROL_START_FLUSH	1	1	0x00000002	0xfffffffd	0x0
L1_IC1_CONTROL_ENABLE_STATS	2	2	0x00000004	0xfffffffb	0x0
L1_IC1_CONTROL_BP_DISABLE	3	3	0x00000008	0xfffffff7	0x0
L1_IC1_CONTROL_RAS_DISABLE	4	4	0x00000010	0xffffffef	0x0
L1_IC1_CONTROL_DISABLE_VLINE	5	6	0x00000060	0xffffff9f	0x0

Register:L1_IC1_PRIORITY (0x7ee02084)

field_name	start_bit	end_bit	set	clear	reset
L1_IC1_PRIORITY_IC1_APRIORITY0	0	3	0x0000000f	0xfffffff0	0xf
L1_IC1_PRIORITY_IC1_APRIORITY1	4	7	0x000000f0	0xffffff0f	0xa
L1_IC1_PRIORITY_IC1_APRIORITY2	8	11	0x00000f00	0xfffff0ff	0x4
L1_IC1_PRIORITY_IC1_APRIORITY3	12	15	0x0000f000	0xffff0fff	0x3

Register:L1_D_CONTROL (0x7ee02100)

field_name	start_bit	end_bit	set	clear	reset
L1_D_CONTROL_DC_DISABLE	0	0	0x00000001	0xfffffffe	0x0
L1_D_CONTROL_DC0_FLUSH	1	1	0x00000002	0xfffffffd	0x0
L1_D_CONTROL_DC1_FLUSH	2	2	0x00000004	0xfffffffb	0x0
L1_D_CONTROL_DC_EN_STATS	3	3	0x00000008	0xfffffff7	0x0

Register:L1_D_PRIORITY (0x7ee0210c)

field_name	start_bit	end_bit	set	clear	reset
L1_D_PRIORITY_c0_l2_priority	0	3	0x0000000f	0xfffffff0	0x0
L1_D_PRIORITY_c0_uc_priority	4	7	0x000000f0	0xffffff0f	0x0
L1_D_PRIORITY_c0_per_priority	8	11	0x00000f00	0xfffff0ff	0x0
missing definiton	12	15	NA	NA	NA
L1_D_PRIORITY_c1_l2_priority	16	19	0x000f0000	0xfff0ffff	0x0
L1_D_PRIORITY_c1_uc_priority	20	23	0x00f00000	0xff0fffff	0x0
L1_D_PRIORITY_c1_per_priority	24	27	0x0f000000	0xf0ffffff	0x0

Register:L1_L1_SANDBOX_START0 (0x7ee02800)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START0_CTRL	0	0	0x00000001	0xfffffffe	0x1
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START0_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START1 (0x7ee02808)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START1_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START1_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START2 (0x7ee02810)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START2_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START2_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START3 (0x7ee02818)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START3_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START3_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START4 (0x7ee02820)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START4_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START4_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START5 (0x7ee02828)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START5_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START5_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START6 (0x7ee02830)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START6_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START6_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_START7 (0x7ee02838)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_START7_CTRL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	4	NA	NA	NA
L1_L1_SANDBOX_START7_START_ADDR	5	29	0x3fffffe0	0xc000001f	0x0

Register:L1_L1_SANDBOX_PERI_BR (0x7ee02840)

field_name	start_bit	end_bit	set	clear	reset
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom	0	4	0x0000001f	0xffffffe0	0x7
missing definiton	5	7	NA	NA	NA
L1_L1_SANDBOX_PERI_BR_sandbox_peri	8	12	0x00001f00	0xffffe0ff	0x7

L2

Info

description	VC4-L2 control
base	0x7ee01000
id	0x4c324343

Registers

register name	address	type	width	mask	reset
L2_CONT_OFF	0x7ee01000	RW	24	0x00ff0c3f	0000000000
L2_FLUSH_STA	0x7ee01004	RW	28	0x0fffffe0	0000000000
L2_FLUSH_END	0x7ee01008	RW	28	0x0fffffe0	0x0fffffe0
L2_L2_ALIAS_EXCEPTION	0x7ee01080	RW			0000000000
L2_L2_ALIAS_EXCEPTION_ID	0x7ee01084	RO			0000000000
L2_L2_ALIAS_EXCEPTION_ADDR	0x7ee01088	RO			0000000000
L2_RD_HITS	0x7ee01100	RW	32	0xffffffff
L2_RD_MISSES	0x7ee01104	RO	32	0xffffffff
L2_WR_HITS	0x7ee01108	RO	32	0xffffffff
L2_WR_MISSES	0x7ee0110c	RO	32	0xffffffff
L2_WR_BACKS	0x7ee01110	RO	32	0xffffffff
L2_IN_FLIGHT	0x7ee01114	RO	4	0x0000000f
L2_STALLS	0x7ee0111c	RO	32	0xffffffff
L2_TAG_STALLS	0x7ee01120	RO	32	0xffffffff
L2_SD_STALLS	0x7ee01124	RO	32	0xffffffff

Register:L2_CONT_OFF (0x7ee01000)

field_name	start_bit	end_bit	set	clear	reset
L2_CONT_OFF_l2_disable	0	0	0x00000001	0xfffffffe	0x0
L2_CONT_OFF_l2_no_wr_allocate	1	1	0x00000002	0xfffffffd	0x0
L2_CONT_OFF_l2_flush	2	2	0x00000004	0xfffffffb	0x0
L2_CONT_OFF_l2_flush_mode	3	4	0x00000018	0xffffffe7	0x0
L2_CONT_OFF_l2_enable_stats	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	9	NA	NA	NA
L2_CONT_OFF_l2_standby	10	11	0x00000c00	0xfffff3ff	0x0
missing definiton	12	15	NA	NA	NA
L2_CONT_OFF_l2_flush_flush_limit	16	19	0x000f0000	0xfff0ffff	0x0
L2_CONT_OFF_l2_flush_core_limit	20	23	0x00f00000	0xff0fffff	0x0

MPHI

Info

base	0x7e006000
id	0x6d706869

Registers

register name	address	type	width	mask
MPHI_C0INDDA	0x7e006000	RW	32	0xffffffff
MPHI_C0INDDB	0x7e006004	RW	32	0xffffffff
MPHI_C1INDDA	0x7e006008	RW	32	0xffffffff
MPHI_C1INDDB	0x7e00600c	RW	32	0xffffffff
MPHI_C0INDS	0x7e006010	RW	32	0xdfffffff
MPHI_C1INDS	0x7e006014	RW	32	0xdfffffff
MPHI_C0INDCF	0x7e006018	RW	32	0xffffffff
MPHI_C1INDCF	0x7e00601c	RW	32	0xffffffff
MPHI_C0INDFS	0x7e006020	RW	32	0xffffffff
MPHI_C1INDFS	0x7e006024	RW	32	0xffffffff
MPHI_OUTDDA	0x7e006028	RW	32	0xffffffff
MPHI_OUTDDB	0x7e00602c	RW	30	0x3fffffff
MPHI_OUTDS	0x7e006030	RW	31	0x5fffffff
MPHI_OUTDFS	0x7e006034	RW	32	0xffffffff
MPHI_MINFS	0x7e006038	RW	32	0xbfffffff
MPHI_MOUTFS	0x7e00603c	RW	32	0xbfffffff
MPHI_AXIPRIV	0x7e006040	RW	9	0x00000177
MPHI_RXAXICFG	0x7e006044	RW	17	0x0001ffff
MPHI_TXAXICFG	0x7e006048	RW	17	0x0001ffff
MPHI_CTRL	0x7e00604c	RW	32	0x88031111
MPHI_INTSTAT	0x7e006050	RW	32	0xf9111111
MPHI_VERSION	0x7e006054	RO	32	0xffffffff
MPHI_INTCTRL	0x7e006058	RW	21	0x00111111
MPHI_HSINDCF	0x7e00605c	RW	32	0xdfffffff
MPHI_HSINDS	0x7e006060	RW	32	0xdfffffff
MPHI_HSINDDA	0x7e006064	RW	32	0xffffffff
MPHI_HSINDDB	0x7e006068	RW	30	0x2fffffff
MPHI_HSINDFS	0x7e00606c	RW	32	0xffff0001

Register:MPHI_C0INDDA (0x7e006000)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C0INDDA_START	0	31	0xffffffff	0x00000000	0x0

Register:MPHI_C0INDDB (0x7e006004)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C0INDDB_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_C0INDDB_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_C0INDDB_MTERM	28	28	0x10000000	0xefffffff	0x0
MPHI_C0INDDB_TENDINT	29	29	0x20000000	0xdfffffff	0x0
MPHI_C0INDDB_MENDINT	30	30	0x40000000	0xbfffffff	0x0
MPHI_C0INDDB_MORUN	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C1INDDA (0x7e006008)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C1INDDA_START	0	31	0xffffffff	0x00000000	0x0

Register:MPHI_C1INDDB (0x7e00600c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C1INDDB_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_C1INDDB_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_C1INDDB_MTERM	28	28	0x10000000	0xefffffff	0x0
MPHI_C1INDDB_TENDINT	29	29	0x20000000	0xdfffffff	0x0
MPHI_C1INDDB_MENDINT	30	30	0x40000000	0xbfffffff	0x0
MPHI_C1INDDB_MORUN	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C0INDS (0x7e006010)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C0INDS_WORDS	0	20	0x001fffff	0xffe00000	0x0
MPHI_C0INDS_HANDLE	21	28	0x1fe00000	0xe01fffff	0x0
missing definiton	29	29	NA	NA	NA
MPHI_C0INDS_VALID	30	30	0x40000000	0xbfffffff	0x0
MPHI_C0INDS_DISCARD	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C1INDS (0x7e006014)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C1INDS_WORDS	0	20	0x001fffff	0xffe00000	0x0
MPHI_C1INDS_HANDLE	21	28	0x1fe00000	0xe01fffff	0x0
missing definiton	29	29	NA	NA	NA
MPHI_C1INDS_VALID	30	30	0x40000000	0xbfffffff	0x0
MPHI_C1INDS_DISCARD	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C0INDCF (0x7e006018)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C0INDCF_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_C0INDCF_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_C0INDCF_MTERM	28	28	0x10000000	0xefffffff	0x0
MPHI_C0INDCF_ORUN	29	29	0x20000000	0xdfffffff	0x0
MPHI_C0INDCF_LENERR	30	30	0x40000000	0xbfffffff	0x0
MPHI_C0INDCF_EMPTY	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C1INDCF (0x7e00601c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C1INDCF_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_C1INDCF_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_C1INDCF_MTERM	28	28	0x10000000	0xefffffff	0x0
MPHI_C1INDCF_ORUN	29	29	0x20000000	0xdfffffff	0x0
MPHI_C1INDCF_LENERR	30	30	0x40000000	0xbfffffff	0x0
MPHI_C1INDCF_EMPTY	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_C0INDFS (0x7e006020)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C0INDFS_DFIFOLVL	0	15	0x0000ffff	0xffff0000	0x0
MPHI_C0INDFS_CFIFOLVL	16	31	0xffff0000	0x0000ffff	0x0

Register:MPHI_C1INDFS (0x7e006024)

field_name	start_bit	end_bit	set	clear	reset
MPHI_C1INDFS_DFIFOLVL	0	15	0x0000ffff	0xffff0000	0x0
MPHI_C1INDFS_CFIFOLVL	16	31	0xffff0000	0x0000ffff	0x0

Register:MPHI_OUTDDA (0x7e006028)

field_name	start_bit	end_bit	set	clear	reset
MPHI_OUTDDA_START	0	31	0xffffffff	0x00000000	0x0

Register:MPHI_OUTDDB (0x7e00602c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_OUTDDB_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_OUTDDB_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_OUTDDB_CHANNEL	28	28	0x10000000	0xefffffff	0x0
MPHI_OUTDDB_TENDINT	29	29	0x20000000	0xdfffffff	0x0

Register:MPHI_OUTDS (0x7e006030)

field_name	start_bit	end_bit	set	clear	reset
MPHI_OUTDS_WORDS	0	20	0x001fffff	0xffe00000	0x0
MPHI_OUTDS_HANDLE	21	28	0x1fe00000	0xe01fffff	0x0
missing definiton	29	29	NA	NA	NA
MPHI_OUTDS_VALID	30	30	0x40000000	0xbfffffff	0x0

Register:MPHI_OUTDFS (0x7e006034)

field_name	start_bit	end_bit	set	clear	reset
MPHI_OUTDFS_DFIFOLVL	0	15	0x0000ffff	0xffff0000	0x0

Register:MPHI_MINFS (0x7e006038)

field_name	start_bit	end_bit	set	clear	reset
MPHI_MINFS_LEVEL	0	9	0x000003ff	0xfffffc00	0x0
MPHI_MINFS_WPTR	10	19	0x000ffc00	0xfff003ff	0x0
MPHI_MINFS_RPTR	20	29	0x3ff00000	0xc00fffff	0x0
missing definiton	30	30	NA	NA	NA
MPHI_MINFS_OFLOW	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_MOUTFS (0x7e00603c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_MOUTFS_LEVEL	0	9	0x000003ff	0xfffffc00	0x0
MPHI_MOUTFS_WPTR	10	19	0x000ffc00	0xfff003ff	0x0
MPHI_MOUTFS_RPTR	20	29	0x3ff00000	0xc00fffff	0x0
missing definiton	30	30	NA	NA	NA
MPHI_MOUTFS_UFLOW	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_AXIPRIV (0x7e006040)

field_name	start_bit	end_bit	set	clear	reset
MPHI_AXIPRIV_TXPROT	0	2	0x00000007	0xfffffff8	0x2
missing definiton	3	3	NA	NA	NA
MPHI_AXIPRIV_RXPROT	4	6	0x00000070	0xffffff8f	0x2
missing definiton	7	7	NA	NA	NA
MPHI_AXIPRIV_HSPECEN	8	8	0x00000100	0xfffffeff	0x0

Register:MPHI_RXAXICFG (0x7e006044)

field_name	start_bit	end_bit	set	clear	reset
MPHI_RXAXICFG_RXNPRIO	0	3	0x0000000f	0xfffffff0	0x0
MPHI_RXAXICFG_RXPPRIO	4	7	0x000000f0	0xffffff0f	0x0
MPHI_RXAXICFG_INTHRESH	8	16	0x0001ff00	0xfffe00ff	0x0

Register:MPHI_TXAXICFG (0x7e006048)

field_name	start_bit	end_bit	set	clear	reset
MPHI_TXAXICFG_TXNPRIO	0	3	0x0000000f	0xfffffff0	0x0
MPHI_TXAXICFG_TXPPRIO	4	7	0x000000f0	0xffffff0f	0x0
MPHI_TXAXICFG_INTHRESH	8	16	0x0001ff00	0xfffe00ff	0x0

Register:MPHI_CTRL (0x7e00604c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_CTRL_HATVAL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	3	NA	NA	NA
MPHI_CTRL_DIRECT	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	7	NA	NA	NA
MPHI_CTRL_INVERT	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
MPHI_CTRL_EIGHTBIT	12	12	0x00001000	0xffffefff	0x1
missing definiton	13	15	NA	NA	NA
MPHI_CTRL_REQ_SOFT_RST	16	16	0x00010000	0xfffeffff	0x0
MPHI_CTRL_SOFT_RST_DNE	17	17	0x00020000	0xfffdffff	0x0
missing definiton	18	26	NA	NA	NA
MPHI_CTRL_STBY	27	27	0x08000000	0xf7ffffff	0x1
missing definiton	28	30	NA	NA	NA
MPHI_CTRL_ENABLE	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_INTSTAT (0x7e006050)

field_name	start_bit	end_bit	set	clear	reset
MPHI_INTSTAT_RX0MEND	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	3	NA	NA	NA
MPHI_INTSTAT_RX0TEND	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	7	NA	NA	NA
MPHI_INTSTAT_RX1MEND	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
MPHI_INTSTAT_RX1TEND	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
MPHI_INTSTAT_TXEND	16	16	0x00010000	0xfffeffff	0x0
missing definiton	17	19	NA	NA	NA
MPHI_INTSTAT_RX0DISC	20	20	0x00100000	0xffefffff	0x0
missing definiton	21	23	NA	NA	NA
MPHI_INTSTAT_RX1DISC	24	24	0x01000000	0xfeffffff	0x0
missing definiton	25	26	NA	NA	NA
MPHI_INTSTAT_HSDCFOFLW	27	27	0x08000000	0xf7ffffff	0x0
MPHI_INTSTAT_OMFUFLW	28	28	0x10000000	0xefffffff	0x0
MPHI_INTSTAT_IMFOFLW	29	29	0x20000000	0xdfffffff	0x0
MPHI_INTSTAT_HSDISC	30	30	0x40000000	0xbfffffff	0x0
MPHI_INTSTAT_HSTEND	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_INTCTRL (0x7e006058)

field_name	start_bit	end_bit	set	clear	reset
MPHI_INTCTRL_RX0DISC	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	3	NA	NA	NA
MPHI_INTCTRL_RX1DISC	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	7	NA	NA	NA
MPHI_INTCTRL_IMFOFLW	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
MPHI_INTCTRL_OMFUFLW	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
MPHI_INTCTRL_HSDISC	16	16	0x00010000	0xfffeffff	0x0
missing definiton	17	19	NA	NA	NA
MPHI_INTCTRL_HSDCOFLW	20	20	0x00100000	0xffefffff	0x0

Register:MPHI_HSINDCF (0x7e00605c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_HSINDCF_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_HSINDCF_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
MPHI_HSINDCF_MTERM	28	28	0x10000000	0xefffffff	0x0
missing definiton	29	29	NA	NA	NA
MPHI_HSINDCF_LENERR	30	30	0x40000000	0xbfffffff	0x0
MPHI_HSINDCF_EMPTY	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_HSINDS (0x7e006060)

field_name	start_bit	end_bit	set	clear	reset
MPHI_HSINDS_WORDS	0	20	0x001fffff	0xffe00000	0x0
MPHI_HSINDS_HANDLE	21	28	0x1fe00000	0xe01fffff	0x0
missing definiton	29	29	NA	NA	NA
MPHI_HSINDS_VALID	30	30	0x40000000	0xbfffffff	0x0
MPHI_HSINDS_DISCARD	31	31	0x80000000	0x7fffffff	0x0

Register:MPHI_HSINDDA (0x7e006064)

field_name	start_bit	end_bit	set	clear	reset
MPHI_HSINDDA_START	0	31	0xffffffff	0x00000000	0x0

Register:MPHI_HSINDDB (0x7e006068)

field_name	start_bit	end_bit	set	clear	reset
MPHI_HSINDDB_LENGTH	0	19	0x000fffff	0xfff00000	0x0
MPHI_HSINDDB_HANDLE	20	27	0x0ff00000	0xf00fffff	0x0
missing definiton	28	28	NA	NA	NA
MPHI_HSINDDB_TENDINT	29	29	0x20000000	0xdfffffff	0x0

Register:MPHI_HSINDFS (0x7e00606c)

field_name	start_bit	end_bit	set	clear	reset
MPHI_HSINDFS_DFIFOLVL	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	15	NA	NA	NA
MPHI_HSINDFS_CFIFOLVL	16	31	0xffff0000	0x0000ffff	0x0

MS

Info

base	0x7e000000
id	0x4d554c54

Registers

register name	address	type	width	mask	reset
MS_SEMA_0	0x7e000000	RW	1	0x00000001	0000000000
MS_SEMA_1	0x7e000004	RW	1	0x00000001	0000000000
MS_SEMA_2	0x7e000008	RW	1	0x00000001	0000000000
MS_SEMA_3	0x7e00000c	RW	1	0x00000001	0000000000
MS_SEMA_4	0x7e000010	RW	1	0x00000001	0000000000
MS_SEMA_5	0x7e000014	RW	1	0x00000001	0000000000
MS_SEMA_6	0x7e000018	RW	1	0x00000001	0000000000
MS_SEMA_7	0x7e00001c	RW	1	0x00000001	0000000000
MS_SEMA_8	0x7e000020	RW	1	0x00000001	0000000000
MS_SEMA_9	0x7e000024	RW	1	0x00000001	0000000000
MS_SEMA_10	0x7e000028	RW	1	0x00000001	0000000000
MS_SEMA_11	0x7e00002c	RW	1	0x00000001	0000000000
MS_SEMA_12	0x7e000030	RW	1	0x00000001	0000000000
MS_SEMA_13	0x7e000034	RW	1	0x00000001	0000000000
MS_SEMA_14	0x7e000038	RW	1	0x00000001	0000000000
MS_SEMA_15	0x7e00003c	RW	1	0x00000001	0000000000
MS_SEMA_16	0x7e000040	RW	1	0x00000001	0000000000
MS_SEMA_17	0x7e000044	RW	1	0x00000001	0000000000
MS_SEMA_18	0x7e000048	RW	1	0x00000001	0000000000
MS_SEMA_19	0x7e00004c	RW	1	0x00000001	0000000000
MS_SEMA_20	0x7e000050	RW	1	0x00000001	0000000000
MS_SEMA_21	0x7e000054	RW	1	0x00000001	0000000000
MS_SEMA_22	0x7e000058	RW	1	0x00000001	0000000000
MS_SEMA_23	0x7e00005c	RW	1	0x00000001	0000000000
MS_SEMA_24	0x7e000060	RW	1	0x00000001	0000000000
MS_SEMA_25	0x7e000064	RW	1	0x00000001	0000000000
MS_SEMA_26	0x7e000068	RW	1	0x00000001	0000000000
MS_SEMA_27	0x7e00006c	RW	1	0x00000001	0000000000
MS_SEMA_28	0x7e000070	RW	1	0x00000001	0000000000
MS_SEMA_29	0x7e000074	RW	1	0x00000001	0000000000
MS_SEMA_30	0x7e000078	RW	1	0x00000001	0000000000
MS_SEMA_31	0x7e00007c	RW	1	0x00000001	0000000000
MS_STATUS	0x7e000080	RO	32	0xffffffff	0000000000
MS_IREQ_0	0x7e000084	RW	32	0xffffffff	0000000000
MS_IREQ_1	0x7e000088	RW	32	0xffffffff	0000000000
MS_ICSET_0	0x7e000090	RW	1	0x00000001	0000000000
MS_ICSET_1	0x7e000094	RW	1	0x00000001	0000000000
MS_ICCLR_0	0x7e000098	RW	1	0x00000001	0000000000
MS_ICCLR_1	0x7e00009c	RW	1	0x00000001	0000000000
MS_MBOX_0	0x7e0000a0	RW	32	0xffffffff	0000000000
MS_MBOX_1	0x7e0000a4	RW	32	0xffffffff	0000000000
MS_MBOX_2	0x7e0000a8	RW	32	0xffffffff	0000000000
MS_MBOX_3	0x7e0000ac	RW	32	0xffffffff	0000000000
MS_MBOX_4	0x7e0000b0	RW	32	0xffffffff	0000000000
MS_MBOX_5	0x7e0000b4	RW	32	0xffffffff	0000000000
MS_MBOX_6	0x7e0000b8	RW	32	0xffffffff	0000000000
MS_MBOX_7	0x7e0000bc	RW	32	0xffffffff	0000000000
MS_VPUSEMA_0	0x7e0000c0	RW
MS_VPUSEMA_1	0x7e0000c4	RW
MS_VPU_STAT	0x7e0000c8	RO	24	0x00ff00ff

Unsupported defines

define	value
MS_DMA	0

Register:MS_SEMA_0 (0x7e000000)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_0_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_1 (0x7e000004)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_1_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_2 (0x7e000008)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_2_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_3 (0x7e00000c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_3_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_4 (0x7e000010)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_4_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_5 (0x7e000014)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_5_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_6 (0x7e000018)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_6_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_7 (0x7e00001c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_7_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_8 (0x7e000020)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_8_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_9 (0x7e000024)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_9_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_10 (0x7e000028)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_10_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_11 (0x7e00002c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_11_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_12 (0x7e000030)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_12_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_13 (0x7e000034)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_13_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_14 (0x7e000038)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_14_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_15 (0x7e00003c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_15_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_16 (0x7e000040)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_16_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_17 (0x7e000044)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_17_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_18 (0x7e000048)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_18_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_19 (0x7e00004c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_19_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_20 (0x7e000050)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_20_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_21 (0x7e000054)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_21_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_22 (0x7e000058)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_22_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_23 (0x7e00005c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_23_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_24 (0x7e000060)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_24_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_25 (0x7e000064)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_25_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_26 (0x7e000068)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_26_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_27 (0x7e00006c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_27_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_28 (0x7e000070)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_28_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_29 (0x7e000074)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_29_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_30 (0x7e000078)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_30_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_SEMA_31 (0x7e00007c)

field_name	start_bit	end_bit	set	clear	reset
MS_SEMA_31_MASK	0	0	0x00000001	0xfffffffe	0x0

Register:MS_STATUS (0x7e000080)

field_name	start_bit	end_bit	set	clear	reset
MS_STATUS_STATUS	0	31	0xffffffff	0x00000000	0x0

Register:MS_IREQ_0 (0x7e000084)

field_name	start_bit	end_bit	set	clear	reset
MS_IREQ_0_IREQ_0	0	31	0xffffffff	0x00000000	0x0

Register:MS_IREQ_1 (0x7e000088)

field_name	start_bit	end_bit	set	clear	reset
MS_IREQ_1_IREQ_1	0	31	0xffffffff	0x00000000	0x0

Register:MS_ICSET_0 (0x7e000090)

field_name	start_bit	end_bit	set	clear	reset
MS_ICSET_0_ICSET_0	0	0	0x00000001	0xfffffffe	0x0

Register:MS_ICSET_1 (0x7e000094)

field_name	start_bit	end_bit	set	clear	reset
MS_ICSET_1_ICSET_1	0	0	0x00000001	0xfffffffe	0x0

Register:MS_ICCLR_0 (0x7e000098)

field_name	start_bit	end_bit	set	clear	reset
MS_ICCLR_0_ICCLR_0	0	0	0x00000001	0xfffffffe	0x0

Register:MS_ICCLR_1 (0x7e00009c)

field_name	start_bit	end_bit	set	clear	reset
MS_ICCLR_1_ICCLR_1	0	0	0x00000001	0xfffffffe	0x0

Register:MS_MBOX_0 (0x7e0000a0)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_0_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_1 (0x7e0000a4)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_1_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_2 (0x7e0000a8)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_2_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_3 (0x7e0000ac)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_3_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_4 (0x7e0000b0)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_4_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_5 (0x7e0000b4)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_5_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_6 (0x7e0000b8)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_6_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_MBOX_7 (0x7e0000bc)

field_name	start_bit	end_bit	set	clear	reset
MS_MBOX_7_MBOX	0	31	0xffffffff	0x00000000	0x0

Register:MS_VPUSEMA_0 (0x7e0000c0)

field_name	start_bit	end_bit	set	clear	reset
MS_VPUSEMA_0_VPUSEMA_0	0	0	0x00000001	0xfffffffe

Register:MS_VPUSEMA_1 (0x7e0000c4)

field_name	start_bit	end_bit	set	clear	reset
MS_VPUSEMA_1_VPUSEMA_1	0	0	0x00000001	0xfffffffe

Register:MS_VPU_STAT (0x7e0000c8)

field_name	start_bit	end_bit	set	clear	reset
MS_VPU_STAT_VPU_STAT	0	0	0x00000001	0xfffffffe

NU

Info

base	0x7e008000

Registers

register name	address	type	width	mask	reset
NU_HOSTIO_OF	0x7e008000	RW	32	0xffffffff	0000000000

OTP

Info

description	One Time programmable
base	0x7e20f000
id	0x206f7470

Registers

register name	address	type	width	mask
OTP_BOOTMODE_REG	0x7e20f000	RW	32	0xffffffff
OTP_CONFIG_REG	0x7e20f004	RW	3	0x00000007
OTP_CTRL_LO_REG	0x7e20f008	RW	32	0xffffffff
OTP_CTRL_HI_REG	0x7e20f00c	RW	16	0x0000ffff
OTP_STATUS_REG	0x7e20f010	RO	32	0xffffffff
OTP_BITSEL_REG	0x7e20f014	RW	5	0x0000001f
OTP_DATA_REG	0x7e20f018	RW	5	0x0000001f
OTP_ADDR_REG	0x7e20f01c	RW	5	0x0000001f
OTP_WRITE_DATA_READ_REG	0x7e20f020	RW	32	0xffffffff
OTP_INIT_STATUS_REG	0x7e20f024	RW	32	0xffffffff

Unsupported defines

define	value
OTP_ARM_DISABLE_BIT	24
OTP_ARM_DISABLE_REDUNDANT_BIT	25
OTP_BASE_ADDRESS	0x7e20f000
OTP_BOOT_EXTRAS_ROW	67
OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS	1
OTP_BOOT_ROM_ROW	17
OTP_BOOT_ROM_ROW_REDUNDANT	18
OTP_BOOT_ROM_SIZE_IN_ROWS	1
OTP_BOOT_SIGNING_KEY_ROW	19
OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT	23
OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS	4
OTP_BOOT_SIGNING_PARITY_ROW	27
OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS	1
OTP_BYTES_PER_ROW	4
OTP_CODE_SIGNING_FLAG_ROW	64
OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS	1
OTP_CODE_SIGNING_KEY_ROW	28
OTP_CODE_SIGNING_KEY_ROW_REDUNDANT	32
OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS	4
OTP_CODE_SIGNING_PARITY_ROW	36
OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS	1
OTP_CONTROL_ROW	16
OTP_CONTROL_SIZE_IN_ROWS	1
OTP_DECRYPTION_ENABLE_FOR_DEBUG	22
OTP_HDCP_AES_KEY_ROW	37
OTP_HDCP_AES_KEY_ROW_REDUNDANT	41
OTP_HDCP_AES_KEY_SIZE_IN_ROWS	4
OTP_HDCP_AES_PARITY_ROW	45
OTP_HDCP_AES_PARITY_SIZE_IN_ROWS	1
OTP_JTAG_DEBUG_KEY_PARITY_START_BIT	0
OTP_JTAG_DEBUG_KEY_ROW	8
OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT	68
OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS	4
OTP_JTAG_DISABLE_BIT	16
OTP_JTAG_DISABLE_REDUNDANT_BIT	17
OTP_JTAG_PARITY_MASK	0xFF
OTP_JTAG_VPU_PARITY_REDUNDANT	76
OTP_MACROVISION_REDUNDANT_START_BIT	20
OTP_MACROVISION_START_BIT	18
OTP_MAX_ROW	65
OTP_MIN_ROW	8
OTP_PRIVATE_KEY_ROW	55
OTP_PRIVATE_KEY_ROW_REDUNDANT	59
OTP_PRIVATE_KEY_SIZE_IN_ROWS	4
OTP_PRIVATE_PARITY_ROW	63
OTP_PRIVATE_PARITY_SIZE_IN_ROWS	1
OTP_PUBLIC_KEY_ROW	46
OTP_PUBLIC_KEY_ROW_REDUNDANT	50
OTP_PUBLIC_KEY_SIZE_IN_ROWS	4
OTP_PUBLIC_PARITY_ROW	54
OTP_PUBLIC_PARITY_SIZE_IN_ROWS	1
OTP_SUSPEND_SECURE_RAM_KEY	65
OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS	2
OTP_VPU_CACHE_KEY_PARITY_START_BIT	8
OTP_VPU_CACHE_KEY_ROW	12
OTP_VPU_CACHE_KEY_ROW_REDUNDANT	72
OTP_VPU_CACHE_KEY_SIZE_IN_ROWS	4
OTP_VPU_CACHE_PARITY_MASK	0xFF

PCM

Info

base	0x7e203000

Registers

register name	address	type	width	mask	reset
PCM_CS_A	0x7e203000	RW	26	0x03ffe3ff	0000000000
PCM_FIFO_A	0x7e203004	RW	32	0xffffffff
PCM_MODE_A	0x7e203008	RW	29	0x1fffffff	0000000000
PCM_RXC_A	0x7e20300c	RW	32	0xffffffff	0000000000
PCM_TXC_A	0x7e203010	RW	32	0xffffffff	0000000000
PCM_DREQ_A	0x7e203014	RW	31	0x7f7f7f7f	0x10303020
PCM_INTEN_A	0x7e203018	RW	4	0x0000000f	0000000000
PCM_INTSTC_A	0x7e20301c	RW	4	0x0000000f	0000000000
PCM_GRAY	0x7e203020	RW	22	0x003ffff7	0000000000

Unsupported defines

define	value
PCM_CH1EN	0x40000000
PCM_CH1POS_LSB	20
PCM_CH1WEX	0x80000000
PCM_CH1WID_LSB	16
PCM_CH2EN	0x4000
PCM_CH2POS_LSB	4
PCM_CH2WEX	0x8000
PCM_CH2WID_LSB	0
PCM_FIFO_DEPTH	64
PCM_POS1(x)	MACRO
PCM_POS2(x)	MACRO
PCM_RX_DMA	0x30000
PCM_TX_DMA	0x20000
PCM_WID1(x)	MACRO
PCM_WID2(x)	MACRO
PCM_WIDTH1(x)	MACRO
PCM_WIDTH2(x)	MACRO

Register:PCM_CS_A (0x7e203000)

field_name	start_bit	end_bit	set	clear	reset
PCM_CS_A_EN	0	0	0x00000001	0xfffffffe	0x0
PCM_CS_A_RXON	1	1	0x00000002	0xfffffffd	0x0
PCM_CS_A_TXON	2	2	0x00000004	0xfffffffb	0x0
PCM_CS_A_TXCLR	3	3	0x00000008	0xfffffff7	0x0
PCM_CS_A_RXCLR	4	4	0x00000010	0xffffffef	0x0
PCM_CS_A_TXTHR	5	6	0x00000060	0xffffff9f	0x0
PCM_CS_A_RXTHR	7	8	0x00000180	0xfffffe7f	0x0
PCM_CS_A_DMAEN	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	12	NA	NA	NA
PCM_CS_A_TXSYNC	13	13	0x00002000	0xffffdfff	0x0
PCM_CS_A_RXSYNC	14	14	0x00004000	0xffffbfff	0x0
PCM_CS_A_TXERR	15	15	0x00008000	0xffff7fff	0x0
PCM_CS_A_RXERR	16	16	0x00010000	0xfffeffff	0x0
PCM_CS_A_TXW	17	17	0x00020000	0xfffdffff	0x0
PCM_CS_A_RXR	18	18	0x00040000	0xfffbffff	0x0
PCM_CS_A_TXD	19	19	0x00080000	0xfff7ffff	0x0
PCM_CS_A_RXD	20	20	0x00100000	0xffefffff	0x0
PCM_CS_A_TXE	21	21	0x00200000	0xffdfffff	0x0
PCM_CS_A_RXF	22	22	0x00400000	0xffbfffff	0x0
PCM_CS_A_RXSEX	23	23	0x00800000	0xff7fffff	0x0
PCM_CS_A_SYNC	24	24	0x01000000	0xfeffffff	0x0
PCM_CS_A_STBY	25	25	0x02000000	0xfdffffff	0x0

Register:PCM_MODE_A (0x7e203008)

field_name	start_bit	end_bit	set	clear	reset
PCM_MODE_A_FSLEN	0	9	0x000003ff	0xfffffc00	0x0
PCM_MODE_A_FLEN	10	19	0x000ffc00	0xfff003ff	0x0
PCM_MODE_A_FSI	20	20	0x00100000	0xffefffff	0x0
PCM_MODE_A_FSM	21	21	0x00200000	0xffdfffff	0x0
PCM_MODE_A_CLKI	22	22	0x00400000	0xffbfffff	0x0
PCM_MODE_A_CLKM	23	23	0x00800000	0xff7fffff	0x0
PCM_MODE_A_FTXP	24	24	0x01000000	0xfeffffff	0x0
PCM_MODE_A_FRXP	25	25	0x02000000	0xfdffffff	0x0
PCM_MODE_A_PDME	26	26	0x04000000	0xfbffffff	0x0
PCM_MODE_A_PDMN	27	27	0x08000000	0xf7ffffff	0x0
PCM_MODE_A_CLK_DIS	28	28	0x10000000	0xefffffff	0x0

Register:PCM_RXC_A (0x7e20300c)

field_name	start_bit	end_bit	set	clear	reset
PCM_RXC_A_CH2WID	0	3	0x0000000f	0xfffffff0	0x0
PCM_RXC_A_CH2POS	4	13	0x00003ff0	0xffffc00f	0x0
PCM_RXC_A_CH2EN	14	14	0x00004000	0xffffbfff	0x0
PCM_RXC_A_CH2WEX	15	15	0x00008000	0xffff7fff	0x0
PCM_RXC_A_CH1WID	16	19	0x000f0000	0xfff0ffff	0x0
PCM_RXC_A_CH1POS	20	29	0x3ff00000	0xc00fffff	0x0
PCM_RXC_A_CH1EN	30	30	0x40000000	0xbfffffff	0x0
PCM_RXC_A_CH1WEX	31	31	0x80000000	0x7fffffff	0x0

Register:PCM_TXC_A (0x7e203010)

field_name	start_bit	end_bit	set	clear	reset
PCM_TXC_A_CH2WID	0	3	0x0000000f	0xfffffff0	0x0
PCM_TXC_A_CH2POS	4	13	0x00003ff0	0xffffc00f	0x0
PCM_TXC_A_CH2EN	14	14	0x00004000	0xffffbfff	0x0
PCM_TXC_A_CH2WEX	15	15	0x00008000	0xffff7fff	0x0
PCM_TXC_A_CH1WID	16	19	0x000f0000	0xfff0ffff	0x0
PCM_TXC_A_CH1POS	20	29	0x3ff00000	0xc00fffff	0x0
PCM_TXC_A_CH1EN	30	30	0x40000000	0xbfffffff	0x0
PCM_TXC_A_CH1WEX	31	31	0x80000000	0x7fffffff	0x0

Register:PCM_DREQ_A (0x7e203014)

field_name	start_bit	end_bit	set	clear	reset
PCM_DREQ_A_RX	0	6	0x0000007f	0xffffff80	0x20
missing definiton	7	7	NA	NA	NA
PCM_DREQ_A_TX	8	14	0x00007f00	0xffff80ff	0x30
missing definiton	15	15	NA	NA	NA
PCM_DREQ_A_RX_PANIC	16	22	0x007f0000	0xff80ffff	0x30
missing definiton	23	23	NA	NA	NA
PCM_DREQ_A_TX_PANIC	24	30	0x7f000000	0x80ffffff	0x10

Register:PCM_INTEN_A (0x7e203018)

field_name	start_bit	end_bit	set	clear	reset
PCM_INTEN_A_TXW	0	0	0x00000001	0xfffffffe	0x0
PCM_INTEN_A_RXR	1	1	0x00000002	0xfffffffd	0x0
PCM_INTEN_A_TXERR	2	2	0x00000004	0xfffffffb	0x0
PCM_INTEN_A_RXERR	3	3	0x00000008	0xfffffff7	0x0

Register:PCM_INTSTC_A (0x7e20301c)

field_name	start_bit	end_bit	set	clear	reset
PCM_INTSTC_A_TXW	0	0	0x00000001	0xfffffffe	0x0
PCM_INTSTC_A_RXR	1	1	0x00000002	0xfffffffd	0x0
PCM_INTSTC_A_TXERR	2	2	0x00000004	0xfffffffb	0x0
PCM_INTSTC_A_RXERR	3	3	0x00000008	0xfffffff7	0x0

Register:PCM_GRAY (0x7e203020)

field_name	start_bit	end_bit	set	clear	reset
PCM_GRAY_EN	0	0	0x00000001	0xfffffffe	0x0
PCM_GRAY_CLR	1	1	0x00000002	0xfffffffd	0x0
PCM_GRAY_FLUSH	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
PCM_GRAY_RXLEVEL	4	9	0x000003f0	0xfffffc0f	0x0
PCM_GRAY_FLUSHED	10	15	0x0000fc00	0xffff03ff	0x0
PCM_GRAY_RXFIFOLEVEL	16	21	0x003f0000	0xffc0ffff	0x0

PIARBCTL

Info

base	0x7e80a000

Registers

register name	address	type	width	mask	reset
PIARBCTL_CAM	0x7e80a000	RW	16	0x0000ffff	0000000000

Register:PIARBCTL_CAM (0x7e80a000)

field_name	start_bit	end_bit	set	clear	reset
PIARBCTL_CAM_LIMIT	0	1	0x00000003	0xfffffffc	0x0
PIARBCTL_CAM_DELAY	2	3	0x0000000c	0xfffffff3	0x0
PIARBCTL_CAM_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
PIARBCTL_CAM_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
PIARBCTL_CAM_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

PIXELVALVE0

Info

base	0x7e206000
id	0x70697876

Registers

register name	address	type	width	mask
PIXELVALVE0_C	0x7e206000	RW	24	0x00ffffff
PIXELVALVE0_VC	0x7e206004	RW	23	0x007fffff
PIXELVALVE0_VSYNCD_EVEN	0x7e206008	RW	17	0x0001ffff
PIXELVALVE0_HORZA	0x7e20600c	RW	32	0xffffffff
PIXELVALVE0_HORZB	0x7e206010	RW	32	0xffffffff
PIXELVALVE0_VERTA	0x7e206014	RW	32	0xffffffff
PIXELVALVE0_VERTB	0x7e206018	RW	32	0xffffffff
PIXELVALVE0_VERTA_EVEN	0x7e20601c	RW	32	0xffffffff
PIXELVALVE0_VERTB_EVEN	0x7e206020	RW	32	0xffffffff
PIXELVALVE0_INTEN	0x7e206024	RW	10	0x000003ff
PIXELVALVE0_INTSTAT	0x7e206028	RW	10	0x000003ff
PIXELVALVE0_STAT	0x7e20602c	RW	10	0x000003ff
PIXELVALVE0_DSI_HACT_ACT	0x7e206030	RW	16	0x0000ffff

PIXELVALVE1

Info

base	0x7e207000
id	0x70697876

Registers

register name	address	type	width	mask
PIXELVALVE1_C	0x7e207000	RW	24	0x00ffffff
PIXELVALVE1_VC	0x7e207004	RW	23	0x007fffff
PIXELVALVE1_VSYNCD_EVEN	0x7e207008	RW	17	0x0001ffff
PIXELVALVE1_HORZA	0x7e20700c	RW	32	0xffffffff
PIXELVALVE1_HORZB	0x7e207010	RW	32	0xffffffff
PIXELVALVE1_VERTA	0x7e207014	RW	32	0xffffffff
PIXELVALVE1_VERTB	0x7e207018	RW	32	0xffffffff
PIXELVALVE1_VERTA_EVEN	0x7e20701c	RW	32	0xffffffff
PIXELVALVE1_VERTB_EVEN	0x7e207020	RW	32	0xffffffff
PIXELVALVE1_INTEN	0x7e207024	RW	10	0x000003ff
PIXELVALVE1_INTSTAT	0x7e207028	RW	10	0x000003ff
PIXELVALVE1_STAT	0x7e20702c	RW	10	0x000003ff
PIXELVALVE1_DSI_HACT_ACT	0x7e207030	RW	16	0x0000ffff

PIXELVALVE2

Info

base	0x7e807000
id	0x70697876

Registers

register name	address	type	width	mask
PIXELVALVE2_C	0x7e807000	RW	24	0x00ffffff
PIXELVALVE2_VC	0x7e807004	RW	23	0x007fffff
PIXELVALVE2_VSYNCD_EVEN	0x7e807008	RW	17	0x0001ffff
PIXELVALVE2_HORZA	0x7e80700c	RW	32	0xffffffff
PIXELVALVE2_HORZB	0x7e807010	RW	32	0xffffffff
PIXELVALVE2_VERTA	0x7e807014	RW	32	0xffffffff
PIXELVALVE2_VERTB	0x7e807018	RW	32	0xffffffff
PIXELVALVE2_VERTA_EVEN	0x7e80701c	RW	32	0xffffffff
PIXELVALVE2_VERTB_EVEN	0x7e807020	RW	32	0xffffffff
PIXELVALVE2_INTEN	0x7e807024	RW	10	0x000003ff
PIXELVALVE2_INTSTAT	0x7e807028	RW	10	0x000003ff
PIXELVALVE2_STAT	0x7e80702c	RW	10	0x000003ff
PIXELVALVE2_DSI_HACT_ACT	0x7e807030	RW	16	0x0000ffff

PM

Info

description	Power manager
base	0x7e100000
id	0x0000706d
password	0x5a000000

Registers

register name	address	type	width	mask	reset
PM_GNRIC	0x7e100000	RW	23	0x007f1fff	0000000000
PM_AUDIO	0x7e100004	RW	22	0x003fffff	0x003000ff
PM_STATUS	0x7e100018	RO	24	0x00ffffff	0000000000
PM_RSTC	0x7e10001c	RW	22	0x00333333	0x00000102
PM_RSTS	0x7e100020	RW	13	0x00001777	0x00001000
PM_WDOG	0x7e100024	RW	20	0x000fffff	0000000000
PM_PADS0	0x7e100028	RW	6	0x0000003f	0x0000001b
PM_PADS2	0x7e10002c	RW	6	0x0000003f	0x0000001b
PM_PADS3	0x7e100030	RW	6	0x0000003f	0x0000001b
PM_PADS4	0x7e100034	RW	6	0x0000003f	0x0000001b
PM_PADS5	0x7e100038	RW	7	0x0000007f	0x0000001b
PM_PADS6	0x7e10003c	RW	9	0x00000123	0000000000
PM_CAM0	0x7e100044	RW	21	0x001fffff	0000000000
PM_CAM1	0x7e100048	RW	21	0x001fffff	0000000000
PM_CCP2TX	0x7e10004c	RW	19	0x0007ffff	0000000000
PM_DSI0	0x7e100050	RW	21	0x001fffff	0000000000
PM_DSI1	0x7e100054	RW	21	0x001fffff	0000000000
PM_HDMI	0x7e100058	RW	20	0x000fffff	0x00080002
PM_USB	0x7e10005c	RW	1	0x00000001	0000000000
PM_PXLDO	0x7e100060	RW	18	0x0003ffff	0000000000
PM_PXBG	0x7e100064	RW	16	0x0000ffff	0000000000
PM_DFT	0x7e100068	RW	2	0x00000003	0000000000
PM_SMPS	0x7e10006c	RW	3	0x00000007	0000000000
PM_XOSC	0x7e100070	RW	1	0x00000001	0000000000
PM_SPAREW	0x7e100074	RW	24	0x00ffffff	0000000000
PM_SPARER	0x7e100078	RO	24	0x00ffffff	0000000000
PM_AVS_RSTDR	0x7e10007c	RW	6	0x0000003f	0000000000
PM_AVS_STAT	0x7e100080	RW	5	0x0000001f	0000000000
PM_AVS_EVENT	0x7e100084	RW	5	0x0000001f	0000000000
PM_AVS_INTEN	0x7e100088	RW	5	0x0000001f	0000000000
PM_DUMMY	0x7e1000fc	RO	1	0x00000001	0x00000001
PM_IMAGE	0x7e100108	RW	23	0x007f11ff	0x00001000
PM_GRAFX	0x7e10010c	RW	23	0x007f107f	0x00001000
PM_PROC	0x7e100110	RW	23	0x007f107f	0000000000

Register:PM_GNRIC (0x7e100000)

field_name	start_bit	end_bit	set	clear	reset
PM_GNRIC_POWUP	0	0	0x00000001	0xfffffffe	0x0
PM_GNRIC_POWOK	1	1	0x00000002	0xfffffffd	0x0
PM_GNRIC_ISPOW	2	2	0x00000004	0xfffffffb	0x0
PM_GNRIC_MEMREP	3	3	0x00000008	0xfffffff7	0x0
PM_GNRIC_MRDONE	4	4	0x00000010	0xffffffef	0x0
PM_GNRIC_ISFUNC	5	5	0x00000020	0xffffffdf	0x0
PM_GNRIC_RSTN	6	11	0x00000fc0	0xfffff03f	0x0
PM_GNRIC_ENAB	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
PM_GNRIC_CFG	16	22	0x007f0000	0xff80ffff	0x0

Register:PM_AUDIO (0x7e100004)

field_name	start_bit	end_bit	set	clear	reset
PM_AUDIO_APSM	0	19	0x000fffff	0xfff00000	0xff
PM_AUDIO_CTRLEN	20	20	0x00100000	0xffefffff	0x1
PM_AUDIO_RSTN	21	21	0x00200000	0xffdfffff	0x1

Register:PM_RSTC (0x7e10001c)

field_name	start_bit	end_bit	set	clear	reset
PM_RSTC_DRCFG	0	1	0x00000003	0xfffffffc	0x2
missing definiton	2	3	NA	NA	NA
PM_RSTC_WRCFG	4	5	0x00000030	0xffffffcf	0x0
missing definiton	6	7	NA	NA	NA
PM_RSTC_SRCFG	8	9	0x00000300	0xfffffcff	0x1
missing definiton	10	11	NA	NA	NA
PM_RSTC_QRCFG	12	13	0x00003000	0xffffcfff	0x0
missing definiton	14	15	NA	NA	NA
PM_RSTC_FRCFG	16	17	0x00030000	0xfffcffff	0x0
missing definiton	18	19	NA	NA	NA
PM_RSTC_HRCFG	20	21	0x00300000	0xffcfffff	0x0

Register:PM_RSTS (0x7e100020)

field_name	start_bit	end_bit	set	clear	reset
PM_RSTS_HADDRQ	0	0	0x00000001	0xfffffffe	0x0
PM_RSTS_HADDRF	1	1	0x00000002	0xfffffffd	0x0
PM_RSTS_HADDRH	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
PM_RSTS_HADWRQ	4	4	0x00000010	0xffffffef	0x0
PM_RSTS_HADWRF	5	5	0x00000020	0xffffffdf	0x0
PM_RSTS_HADWRH	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	7	NA	NA	NA
PM_RSTS_HADSRQ	8	8	0x00000100	0xfffffeff	0x0
PM_RSTS_HADSRF	9	9	0x00000200	0xfffffdff	0x0
PM_RSTS_HADSRH	10	10	0x00000400	0xfffffbff	0x0
missing definiton	11	11	NA	NA	NA
PM_RSTS_HADPOR	12	12	0x00001000	0xffffefff	0x1

Register:PM_WDOG (0x7e100024)

field_name	start_bit	end_bit	set	clear	reset
PM_WDOG_TIME	0	19	0x000fffff	0xfff00000	0x0

Register:PM_PADS0 (0x7e100028)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS0_DRIVE	0	2	0x00000007	0xfffffff8	0x3
PM_PADS0_HYST	3	3	0x00000008	0xfffffff7	0x1
PM_PADS0_SLEW	4	4	0x00000010	0xffffffef	0x1
PM_PADS0_POWOK	5	5	0x00000020	0xffffffdf	0x0

Register:PM_PADS2 (0x7e10002c)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS2_DRIVE	0	2	0x00000007	0xfffffff8	0x3
PM_PADS2_HYST	3	3	0x00000008	0xfffffff7	0x1
PM_PADS2_SLEW	4	4	0x00000010	0xffffffef	0x1
PM_PADS2_POWOK	5	5	0x00000020	0xffffffdf	0x0

Register:PM_PADS3 (0x7e100030)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS3_DRIVE	0	2	0x00000007	0xfffffff8	0x3
PM_PADS3_HYST	3	3	0x00000008	0xfffffff7	0x1
PM_PADS3_SLEW	4	4	0x00000010	0xffffffef	0x1
PM_PADS3_POWOK	5	5	0x00000020	0xffffffdf	0x0

Register:PM_PADS4 (0x7e100034)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS4_DRIVE	0	2	0x00000007	0xfffffff8	0x3
PM_PADS4_HYST	3	3	0x00000008	0xfffffff7	0x1
PM_PADS4_SPARE	4	4	0x00000010	0xffffffef	0x1
PM_PADS4_POWOK	5	5	0x00000020	0xffffffdf	0x0

Register:PM_PADS5 (0x7e100038)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS5_DRIVE	0	2	0x00000007	0xfffffff8	0x3
PM_PADS5_HYST	3	3	0x00000008	0xfffffff7	0x1
PM_PADS5_SLEW	4	4	0x00000010	0xffffffef	0x1
PM_PADS5_POWOK	5	5	0x00000020	0xffffffdf	0x0
PM_PADS5_I2CMODE	6	6	0x00000040	0xffffffbf	0x0

Register:PM_PADS6 (0x7e10003c)

field_name	start_bit	end_bit	set	clear	reset
PM_PADS6_DRIVE	0	1	0x00000003	0xfffffffc	0x0
missing definiton	2	4	NA	NA	NA
PM_PADS6_POWOK	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	7	NA	NA	NA
PM_PADS6_PD	8	8	0x00000100	0xfffffeff	0x0

Register:PM_CAM0 (0x7e100044)

field_name	start_bit	end_bit	set	clear	reset
PM_CAM0_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_CAM0_LDOLPEN	1	1	0x00000002	0xfffffffd	0x0
PM_CAM0_LDOHPEN	2	2	0x00000004	0xfffffffb	0x0
PM_CAM0_LDOCTRL	3	20	0x001ffff8	0xffe00007	0x0

Register:PM_CAM1 (0x7e100048)

field_name	start_bit	end_bit	set	clear	reset
PM_CAM1_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_CAM1_LDOLPEN	1	1	0x00000002	0xfffffffd	0x0
PM_CAM1_LDOHPEN	2	2	0x00000004	0xfffffffb	0x0
PM_CAM1_LDOCTRL	3	20	0x001ffff8	0xffe00007	0x0

Register:PM_CCP2TX (0x7e10004c)

field_name	start_bit	end_bit	set	clear	reset
PM_CCP2TX_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_CCP2TX_LDOEN	1	1	0x00000002	0xfffffffd	0x0
PM_CCP2TX_LDOCTRL	2	18	0x0007fffc	0xfff80003	0x0

Register:PM_DSI0 (0x7e100050)

field_name	start_bit	end_bit	set	clear	reset
PM_DSI0_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_DSI0_LDOLPEN	1	1	0x00000002	0xfffffffd	0x0
PM_DSI0_LDOHPEN	2	2	0x00000004	0xfffffffb	0x0
PM_DSI0_LDOCTRL	3	20	0x001ffff8	0xffe00007	0x0

Register:PM_DSI1 (0x7e100054)

field_name	start_bit	end_bit	set	clear	reset
PM_DSI1_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_DSI1_LDOLPEN	1	1	0x00000002	0xfffffffd	0x0
PM_DSI1_LDOHPEN	2	2	0x00000004	0xfffffffb	0x0
PM_DSI1_LDOCTRL	3	20	0x001ffff8	0xffe00007	0x0

Register:PM_HDMI (0x7e100058)

field_name	start_bit	end_bit	set	clear	reset
PM_HDMI_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_HDMI_LDOPD	1	1	0x00000002	0xfffffffd	0x1
PM_HDMI_LDOCTRL	2	18	0x0007fffc	0xfff80003	0x0
PM_HDMI_RSTDR	19	19	0x00080000	0xfff7ffff	0x1

Register:PM_USB (0x7e10005c)

field_name	start_bit	end_bit	set	clear	reset
PM_USB_CTRLEN	0	0	0x00000001	0xfffffffe	0x0

Register:PM_PXLDO (0x7e100060)

field_name	start_bit	end_bit	set	clear	reset
PM_PXLDO_CTRL	0	15	0x0000ffff	0xffff0000	0x0
PM_PXLDO_RSTOSCDR	16	16	0x00010000	0xfffeffff	0x0
PM_PXLDO_RSTPLLDR	17	17	0x00020000	0xfffdffff	0x0

Register:PM_PXBG (0x7e100064)

field_name	start_bit	end_bit	set	clear	reset
PM_PXBG_CTRL	0	15	0x0000ffff	0xffff0000	0x0

Register:PM_DFT (0x7e100068)

field_name	start_bit	end_bit	set	clear	reset
PM_DFT_ALLOWAUDIOCKSTOP	0	0	0x00000001	0xfffffffe	0x0
PM_DFT_STOPALLCLOCKS	1	1	0x00000002	0xfffffffd	0x0

Register:PM_SMPS (0x7e10006c)

field_name	start_bit	end_bit	set	clear	reset
PM_SMPS_CTRLEN	0	0	0x00000001	0xfffffffe	0x0
PM_SMPS_RSTDR	1	1	0x00000002	0xfffffffd	0x0
PM_SMPS_UPEN	2	2	0x00000004	0xfffffffb	0x0

Register:PM_XOSC (0x7e100070)

field_name	start_bit	end_bit	set	clear	reset
PM_XOSC_USESEC	0	0	0x00000001	0xfffffffe	0x0

Register:PM_SPAREW (0x7e100074)

field_name	start_bit	end_bit	set	clear	reset
PM_SPAREW_SPARE	0	23	0x00ffffff	0xff000000	0x0

Register:PM_SPARER (0x7e100078)

field_name	start_bit	end_bit	set	clear	reset
PM_SPARER_SPARE	0	23	0x00ffffff	0xff000000	0x0

Register:PM_AVS_RSTDR (0x7e10007c)

field_name	start_bit	end_bit	set	clear	reset
PM_AVS_RSTDR_PERI_A	0	0	0x00000001	0xfffffffe	0x0
PM_AVS_RSTDR_SYSTEM_A	1	1	0x00000002	0xfffffffd	0x0
PM_AVS_RSTDR_H264_I	2	2	0x00000004	0xfffffffb	0x0
PM_AVS_RSTDR_V3D_G	3	3	0x00000008	0xfffffff7	0x0
PM_AVS_RSTDR_ARM_P	4	4	0x00000010	0xffffffef	0x0
PM_AVS_RSTDR_ROSC	5	5	0x00000020	0xffffffdf	0x0

Register:PM_AVS_STAT (0x7e100080)

field_name	start_bit	end_bit	set	clear	reset
PM_AVS_STAT_ALERT_PERI_A	0	0	0x00000001	0xfffffffe	0x0
PM_AVS_STAT_ALERT_SYSTEM_A	1	1	0x00000002	0xfffffffd	0x0
PM_AVS_STAT_ALERT_H264_I	2	2	0x00000004	0xfffffffb	0x0
PM_AVS_STAT_ALERT_V3D_G	3	3	0x00000008	0xfffffff7	0x0
PM_AVS_STAT_ALERT_ARM_P	4	4	0x00000010	0xffffffef	0x0

Register:PM_AVS_EVENT (0x7e100084)

field_name	start_bit	end_bit	set	clear	reset
PM_AVS_EVENT_ALERT_PERI_A	0	0	0x00000001	0xfffffffe	0x0
PM_AVS_EVENT_ALERT_SYSTEM_A	1	1	0x00000002	0xfffffffd	0x0
PM_AVS_EVENT_ALERT_H264_I	2	2	0x00000004	0xfffffffb	0x0
PM_AVS_EVENT_ALERT_V3D_G	3	3	0x00000008	0xfffffff7	0x0
PM_AVS_EVENT_ALERT_ARM_P	4	4	0x00000010	0xffffffef	0x0

Register:PM_AVS_INTEN (0x7e100088)

field_name	start_bit	end_bit	set	clear	reset
PM_AVS_INTEN_ALERT_PERI_A	0	0	0x00000001	0xfffffffe	0x0
PM_AVS_INTEN_ALERT_SYSTEM_A	1	1	0x00000002	0xfffffffd	0x0
PM_AVS_INTEN_ALERT_H264_I	2	2	0x00000004	0xfffffffb	0x0
PM_AVS_INTEN_ALERT_V3D_G	3	3	0x00000008	0xfffffff7	0x0
PM_AVS_INTEN_ALERT_ARM_P	4	4	0x00000010	0xffffffef	0x0

Register:PM_DUMMY (0x7e1000fc)

field_name	start_bit	end_bit	set	clear	reset
PM_DUMMY_ONE	0	0	0x00000001	0xfffffffe	0x1

Register:PM_IMAGE (0x7e100108)

field_name	start_bit	end_bit	set	clear	reset
PM_IMAGE_POWUP	0	0	0x00000001	0xfffffffe	0x0
PM_IMAGE_POWOK	1	1	0x00000002	0xfffffffd	0x0
PM_IMAGE_ISPOW	2	2	0x00000004	0xfffffffb	0x0
PM_IMAGE_MEMREP	3	3	0x00000008	0xfffffff7	0x0
PM_IMAGE_MRDONE	4	4	0x00000010	0xffffffef	0x0
PM_IMAGE_ISFUNC	5	5	0x00000020	0xffffffdf	0x0
PM_IMAGE_PERIRSTN	6	6	0x00000040	0xffffffbf	0x0
PM_IMAGE_H264RSTN	7	7	0x00000080	0xffffff7f	0x0
PM_IMAGE_ISPRSTN	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
PM_IMAGE_ENAB	12	12	0x00001000	0xffffefff	0x1
missing definiton	13	15	NA	NA	NA
PM_IMAGE_CFG	16	22	0x007f0000	0xff80ffff	0x0

Register:PM_GRAFX (0x7e10010c)

field_name	start_bit	end_bit	set	clear	reset
PM_GRAFX_POWUP	0	0	0x00000001	0xfffffffe	0x0
PM_GRAFX_POWOK	1	1	0x00000002	0xfffffffd	0x0
PM_GRAFX_ISPOW	2	2	0x00000004	0xfffffffb	0x0
PM_GRAFX_MEMREP	3	3	0x00000008	0xfffffff7	0x0
PM_GRAFX_MRDONE	4	4	0x00000010	0xffffffef	0x0
PM_GRAFX_ISFUNC	5	5	0x00000020	0xffffffdf	0x0
PM_GRAFX_V3DRSTN	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	11	NA	NA	NA
PM_GRAFX_ENAB	12	12	0x00001000	0xffffefff	0x1
missing definiton	13	15	NA	NA	NA
PM_GRAFX_CFG	16	22	0x007f0000	0xff80ffff	0x0

Register:PM_PROC (0x7e100110)

field_name	start_bit	end_bit	set	clear	reset
PM_PROC_POWUP	0	0	0x00000001	0xfffffffe	0x0
PM_PROC_POWOK	1	1	0x00000002	0xfffffffd	0x0
PM_PROC_ISPOW	2	2	0x00000004	0xfffffffb	0x0
PM_PROC_MEMREP	3	3	0x00000008	0xfffffff7	0x0
PM_PROC_MRDONE	4	4	0x00000010	0xffffffef	0x0
PM_PROC_ISFUNC	5	5	0x00000020	0xffffffdf	0x0
PM_PROC_ARMRSTN	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	11	NA	NA	NA
PM_PROC_ENAB	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
PM_PROC_CFG	16	22	0x007f0000	0xff80ffff	0x0

PRM

Info

base	0x7e20d000

Registers

register name	address	type	width	mask
PRM_CS	0x7e20d000	RW	32	0xffffffff
PRM_CV	0x7e20d004	RW	32	0xffffffff
PRM_SCC	0x7e20d008	RW	32	0xffffffff

PWM

Info

base	0x7e20c000
id	0x70776d30

Registers

register name	address	type	width	mask	reset
PWM_CTL	0x7e20c000	RW	32	0xbfbfbfff	0000000000
PWM_STA	0x7e20c004	RW	13	0x00001fff	0000000000
PWM_DMAC	0x7e20c008	RW	32	0x8000ffff	0x00000707
PWM_RNG1	0x7e20c010	RW	32	0xffffffff	0x00000020
PWM_DAT1	0x7e20c014	RW	32	0xffffffff	0000000000
PWM_FIF1	0x7e20c018	RW	32	0xffffffff	0000000000
PWM_RNG2	0x7e20c020	RW	32	0xffffffff	0x00000020
PWM_DAT2	0x7e20c024	RW	32	0xffffffff	0000000000
PWM_RNG3	0x7e20c030	RW	0	0000000000	0x00000020
PWM_DAT3	0x7e20c034	RW	0	0000000000	0000000000
PWM_RNG4	0x7e20c040	RW	0	0000000000	0x00000020
PWM_DAT4	0x7e20c044	RW	0	0000000000	0000000000

Unsupported defines

define	value
PWM_BASE_ADDRESS	0x7e20c000
PWM_DMA	0x50000

Register:PWM_CTL (0x7e20c000)

field_name	start_bit	end_bit	set	clear	reset
PWM_CTL_PWEN1	0	0	0x00000001	0xfffffffe	0x0
PWM_CTL_MODE1	1	1	0x00000002	0xfffffffd	0x0
PWM_CTL_RPTL1	2	2	0x00000004	0xfffffffb	0x0
PWM_CTL_SBIT1	3	3	0x00000008	0xfffffff7	0x0
PWM_CTL_POLA1	4	4	0x00000010	0xffffffef	0x0
PWM_CTL_USEF1	5	5	0x00000020	0xffffffdf	0x0
PWM_CTL_CLRF1	6	6	0x00000040	0xffffffbf	0x0
PWM_CTL_MSEN1	7	7	0x00000080	0xffffff7f	0x0
PWM_CTL_PWEN2	8	8	0x00000100	0xfffffeff	0x0
PWM_CTL_MODE2	9	9	0x00000200	0xfffffdff	0x0
PWM_CTL_RPTL2	10	10	0x00000400	0xfffffbff	0x0
PWM_CTL_SBIT2	11	11	0x00000800	0xfffff7ff	0x0
PWM_CTL_POLA2	12	12	0x00001000	0xffffefff	0x0
PWM_CTL_USEF2	13	13	0x00002000	0xffffdfff	0x0
missing definiton	14	14	NA	NA	NA
PWM_CTL_MSEN2	15	15	0x00008000	0xffff7fff	0x0
PWM_CTL_PWEN3	16	16	0x00010000	0xfffeffff	0x0
PWM_CTL_MODE3	17	17	0x00020000	0xfffdffff	0x0
PWM_CTL_RPTL3	18	18	0x00040000	0xfffbffff	0x0
PWM_CTL_SBIT3	19	19	0x00080000	0xfff7ffff	0x0
PWM_CTL_POLA3	20	20	0x00100000	0xffefffff	0x0
PWM_CTL_USEF3	21	21	0x00200000	0xffdfffff	0x0
missing definiton	22	22	NA	NA	NA
PWM_CTL_MSEN3	23	23	0x00800000	0xff7fffff	0x0
PWM_CTL_PWEN4	24	24	0x01000000	0xfeffffff	0x0
PWM_CTL_MODE4	25	25	0x02000000	0xfdffffff	0x0
PWM_CTL_RPTL4	26	26	0x04000000	0xfbffffff	0x0
PWM_CTL_SBIT4	27	27	0x08000000	0xf7ffffff	0x0
PWM_CTL_POLA4	28	28	0x10000000	0xefffffff	0x0
PWM_CTL_USEF4	29	29	0x20000000	0xdfffffff	0x0
missing definiton	30	30	NA	NA	NA
PWM_CTL_MSEN4	31	31	0x80000000	0x7fffffff	0x0

Register:PWM_STA (0x7e20c004)

field_name	start_bit	end_bit	set	clear	reset
PWM_STA_FULL1	0	0	0x00000001	0xfffffffe	0x0
PWM_STA_EMPT1	1	1	0x00000002	0xfffffffd	0x0
PWM_STA_WERR1	2	2	0x00000004	0xfffffffb	0x0
PWM_STA_RERR1	3	3	0x00000008	0xfffffff7	0x0
PWM_STA_GAPO1	4	4	0x00000010	0xffffffef	0x0
PWM_STA_GAPO2	5	5	0x00000020	0xffffffdf	0x0
PWM_STA_GAPO3	6	6	0x00000040	0xffffffbf	0x0
PWM_STA_GAPO4	7	7	0x00000080	0xffffff7f	0x0
PWM_STA_BERR	8	8	0x00000100	0xfffffeff	0x0
PWM_STA_STA1	9	9	0x00000200	0xfffffdff	0x0
PWM_STA_STA2	10	10	0x00000400	0xfffffbff	0x0
PWM_STA_STA3	11	11	0x00000800	0xfffff7ff	0x0
PWM_STA_STA4	12	12	0x00001000	0xffffefff	0x0

Register:PWM_DMAC (0x7e20c008)

field_name	start_bit	end_bit	set	clear	reset
PWM_DMAC_DREQ	0	7	0x000000ff	0xffffff00	0x7
PWM_DMAC_PANIC	8	15	0x0000ff00	0xffff00ff	0x7
missing definiton	16	30	NA	NA	NA
PWM_DMAC_ENAB	31	31	0x80000000	0x7fffffff	0x0

RNG

Info

base	0x7e104000
id	0x20726e67

Registers

register name	address	type	width	mask
RNG_CTRL	0x7e104000	RW	32	0xffffffff
RNG_STATUS	0x7e104004	RW	32	0xffffffff
RNG_DATA	0x7e104008	RW	32	0xffffffff
RNG_FF_THRESHOLD	0x7e10400c	RW	32	0xffffffff
RNG_INT_MASK	0x7e104010	RW	32	0xffffffff

SCALER

Info

base	0x7e400000
id	0x64647276

Registers

register name	address	type	width	mask	reset
SCALER_DISPCTRL	0x7e400000	RW	32	0xffffffff
SCALER_INPUT_CONTROL	0x7e400000	RW
SCALER_IRQ_STATUS	0x7e400004	RW
SCALER_DISPSTAT	0x7e400004	RW	32	0xffffffff
SCALER_DISPID	0x7e400008	RW	32	0xffffffff	0x64647276
SCALER_ID	0x7e400008	RW
SCALER_DISPECTRL	0x7e40000c	RW	32	0xffffffff
SCALER_ALT_CONTROL	0x7e40000c	RW
SCALER_PROFILE	0x7e400010	RW
SCALER_DISPPROF	0x7e400010	RW	32	0xffffffff
SCALER_DISPDITHER	0x7e400014	RW	32	0xffffffff
SCALER_DITHER	0x7e400014	RW
SCALER_DISPEOLN	0x7e400018	RW	32	0xffffffff
SCALER_DISPLIST0	0x7e400020	RW	32	0xffffffff
SCALER_DISP_LIST_0	0x7e400020	RW
SCALER_DISPLIST1	0x7e400024	RW	32	0xffffffff
SCALER_DISP_LIST_1	0x7e400024	RW
SCALER_DISPLIST2	0x7e400028	RW	32	0xffffffff
SCALER_DISP_LIST_2	0x7e400028	RW
SCALER_DISPLSTAT	0x7e40002c	RW	32	0xffffffff
SCALER_DISP_LIST_STATUS	0x7e40002c	RW
SCALER_DISPLACT0	0x7e400030	RW	32	0xffffffff
SCALER_DISPLACT1	0x7e400034	RW	32	0xffffffff
SCALER_DISPLACT2	0x7e400038	RW	32	0xffffffff
SCALER_DISPCTL_0	0x7e400040	RW
SCALER_DISPCTRL0	0x7e400040	RW	32	0xffffffff
SCALER_DISPBKGND_0	0x7e400044	RW
SCALER_DISPBKGND0	0x7e400044	RW	32	0xffffffff
SCALER_DISPSTAT_0	0x7e400048	RW
SCALER_DISPSTAT0	0x7e400048	RW	32	0xffffffff
SCALER_DISPBASE0	0x7e40004c	RW	32	0xffffffff
SCALER_DISPCTRL1	0x7e400050	RW	32	0xffffffff
SCALER_DISPCTL_1	0x7e400050	RW
SCALER_DISPBKGND_1	0x7e400054	RW
SCALER_DISPBKGND1	0x7e400054	RW	32	0xffffffff
SCALER_DISPSTAT1	0x7e400058	RW	32	0xffffffff
SCALER_DISPSTAT_1	0x7e400058	RW
SCALER_DISPBASE_1	0x7e40005c	RW
SCALER_DISPBASE1	0x7e40005c	RW	32	0xffffffff
SCALER_DISPCTL_2	0x7e400060	RW
SCALER_DISPCTRL2	0x7e400060	RW	32	0xffffffff
SCALER_DISPBKGND2	0x7e400064	RW	32	0xffffffff
SCALER_DISPBKGND_2	0x7e400064	RW
SCALER_DISPSTAT_2	0x7e400068	RW
SCALER_DISPSTAT2	0x7e400068	RW	32	0xffffffff
SCALER_DISPBASE_2	0x7e40006c	RW
SCALER_DISPBASE2	0x7e40006c	RW	32	0xffffffff
SCALER_DISPALPHA2	0x7e400070	RW	32	0xffffffff
SCALER_GAM_ADDRESS	0x7e400078	RW
SCALER_DISPGAMADR	0x7e400078	RW	32	0xffffffff
SCALER_OLEDOFFS	0x7e400080	RW	32	0xffffffff
SCALER_OLEDCOEF0	0x7e400084	RW	32	0xffffffff
SCALER_OLEDCOEF1	0x7e400088	RW	32	0xffffffff
SCALER_OLEDCOEF2	0x7e40008c	RW	32	0xffffffff
SCALER_DISPSLAVE0	0x7e4000c0	RW	32	0xffffffff
SCALER_DISPSLAVE1	0x7e4000c8	RW	32	0xffffffff
SCALER_DISPSLAVE2	0x7e4000d0	RW	32	0xffffffff
SCALER_GAM_DATA	0x7e4000e0	RW
SCALER_DISPGAMDAT	0x7e4000e0	RW	32	0xffffffff

Unsupported defines

define	value
SCALER_0_DMA	0x150000
SCALER_1_DMA	0x160000
SCALER_2_DMA	0x170000
SCALER_BASE_ADDRESS	0x7e400000
SCALER_COB_FIFO_SIZE	(0x4000)
SCALER_CONTEXT_MEMORY_START	0x7e402000
SCALER_CONTEXT_MEM_SIZE	( 1024 * 16 )
SCALER_LINE_BUFFER_MEM_SIZE	( 1024 * 64 )

Register:SCALER_DISPCTRL (0x7e400000)

field_name	start_bit	end_bit	set	clear	reset
SCALER_DISPCTRL_IRQ_EN	0	6	0x0000007f	0xffffff80
missing definiton	7	8	NA	NA	NA
SCALER_DISPCTRL_DSP1_IRQ_CTRL	9	10	0x00000600	0xfffff9ff
SCALER_DISPCTRL_DSP2_IRQ_CTRL	11	12	0x00001800	0xffffe7ff
missing definiton	13	15	NA	NA	NA
SCALER_DISPCTRL_TILE_WID	16	17	0x00030000	0xfffcffff
SCALER_DISPCTRL_DSP3_MUX	18	19	0x000c0000	0xfff3ffff
missing definiton	20	23	NA	NA	NA
SCALER_DISPCTRL_DSP0_PANIC	24	25	0x03000000	0xfcffffff
SCALER_DISPCTRL_DSP1_PANIC	26	27	0x0c000000	0xf3ffffff
SCALER_DISPCTRL_DSP2_PANIC	28	29	0x30000000	0xcfffffff
SCALER_DISPCTRL_VSCL_DIS	30	31	0xc0000000	0x3fffffff
SCALER_DISPCTRL_HVS_EN	31	31	0x80000000	0x7fffffff
missing definiton	32	30	NA	NA	NA

Register:SCALER_DISPSTAT (0x7e400004)

field_name	start_bit	end_bit	set	clear	reset
SCALER_DISPSTAT_PROF_IRQ	0	31	0xffffffff	0x00000000
SCALER_DISPSTAT_DSP0_IRQ	1	31	0xfffffffe	0x00000001
SCALER_DISPSTAT_DSP1_IRQ	2	31	0xfffffffc	0x00000003
SCALER_DISPSTAT_DSP2_IRQ	3	31	0xfffffff8	0x00000007
SCALER_DISPSTAT_DMA_IRQ	4	31	0xfffffff0	0x0000000f
SCALER_DISPSTAT_WR_IRQ	5	31	0xffffffe0	0x0000001f
SCALER_DISPSTAT_RD_IRQ	6	31	0xffffffc0	0x0000003f
SCALER_DISPSTAT_DMA_ERR_BIT2	7	31	0xffffff80	0x0000007f
SCALER_DISPSTAT_DSP0_STATUS	8	13	0x00003f00	0xffffc0ff
SCALER_DISPSTAT_DMA_ERR_BIT0	14	31	0xffffc000	0x00003fff
SCALER_DISPSTAT_DMA_ERR_BIT1	15	31	0xffff8000	0x00007fff
SCALER_DISPSTAT_DSP1_STATUS	16	21	0x003f0000	0xffc0ffff
missing definiton	22	23	NA	NA	NA
SCALER_DISPSTAT_DSP2_STATUS	24	29	0x3f000000	0xc0ffffff
missing definiton	32	4	NA	NA	NA
missing definiton	32	15	NA	NA	NA
missing definiton	32	3	NA	NA	NA
missing definiton	32	7	NA	NA	NA
missing definiton	32	5	NA	NA	NA
missing definiton	32	2	NA	NA	NA
missing definiton	32	0	NA	NA	NA
missing definiton	32	6	NA	NA	NA
missing definiton	32	1	NA	NA	NA
missing definiton	32	14	NA	NA	NA

Register:SCALER_DISPECTRL (0x7e40000c)

field_name	start_bit	end_bit	set	clear	reset
SCALER_DISPECTRL_PANIC_CTRL	0	6	0x0000007f	0xffffff80
missing definiton	7	7	NA	NA	NA
SCALER_DISPECTRL_BUSY_STATUS	8	31	0xffffff00	0x000000ff
SCALER_DISPECTRL_Y_BUSY	9	31	0xfffffe00	0x000001ff
SCALER_DISPECTRL_CB_BUSY	10	31	0xfffffc00	0x000003ff
SCALER_DISPECTRL_CR_BUSY	11	31	0xfffff800	0x000007ff
SCALER_DISPECTRL_POSTED_STATUS	12	14	0x00007000	0xffff8fff
missing definiton	15	15	NA	NA	NA
SCALER_DISPECTRL_POSTED_CTRL	16	21	0x003f0000	0xffc0ffff
missing definiton	22	23	NA	NA	NA
SCALER_DISPECTRL_GT8_BURST	24	31	0xff000000	0x00ffffff
SCALER_DISPECTRL_TWOD_SINGLE	25	31	0xfe000000	0x01ffffff
SCALER_DISPECTRL_PROF_TYPE	26	27	0x0c000000	0xf3ffffff
SCALER_DISPECTRL_Y_NE_CTRL	28	31	0xf0000000	0x0fffffff
SCALER_DISPECTRL_CB_NE_CTRL	29	31	0xe0000000	0x1fffffff
SCALER_DISPECTRL_CR_NE_CTRL	30	31	0xc0000000	0x3fffffff
SCALER_DISPECTRL_SECURE_MODE	31	31	0x80000000	0x7fffffff
missing definiton	32	8	NA	NA	NA
missing definiton	32	28	NA	NA	NA
missing definiton	32	9	NA	NA	NA
missing definiton	32	11	NA	NA	NA
missing definiton	32	10	NA	NA	NA
missing definiton	32	25	NA	NA	NA
missing definiton	32	29	NA	NA	NA
missing definiton	32	24	NA	NA	NA
missing definiton	32	30	NA	NA	NA

SD

Info

description	SDRAM
base	0x7ee00000
id	0x5344434f

Registers

register name	address	type	width	mask	reset
SD_CS	0x7ee00000	RW	25	0x01ffffff
SD_SA	0x7ee00004	RW	32	0xffffffff
SD_SB	0x7ee00008	RW	32	0xfff001ff
SD_SC	0x7ee0000c	RW	31	0x7ff00f77
SD_PT2	0x7ee00010	RW	32	0xffffffff
SD_PT1	0x7ee00014	RW	28	0x0fffffff
SD_IDL	0x7ee00018	RW	28	0x0fffffff	0000000000
SD_RTC	0x7ee0001c	RW	32	0xffffffff	0000000000
SD_WTC	0x7ee00020	RO	28	0x0fffffff	0000000000
SD_RDC	0x7ee00024	RO	28	0x0fffffff	0000000000
SD_WDC	0x7ee00028	RO	28	0x0fffffff	0000000000
SD_RAC	0x7ee0002c	RO	28	0x0fffffff	0000000000
SD_CYC	0x7ee00030	RO	28	0x0fffffff	0000000000
SD_CMD	0x7ee00034	RO	28	0x0fffffff	0000000000
SD_DAT	0x7ee00038	RO	28	0x0fffffff	0000000000
SD_SECSRT0	0x7ee0003c	RW	32	0xffffffff
SD_SECEND0	0x7ee00040	RW	32	0xffffffff
SD_SECSRT1	0x7ee00044	RW	32	0xffffffff
SD_SECEND1	0x7ee00048	RW	32	0xffffffff
SD_SECSRT2	0x7ee0004c	RW	32	0xffffffff
SD_SECEND2	0x7ee00050	RW	32	0xffffffff
SD_SECSRT3	0x7ee00054	RW	32	0xffffffff
SD_SECEND3	0x7ee00058	RW	32	0xffffffff
SD_PHYC	0x7ee00060	RW	25	0x01111111
SD_MRT	0x7ee00064	RW	9	0x000001ff
SD_TMC	0x7ee0007c	RW	32	0xffffff73
SD_RWC	0x7ee00080	RW	32	0x9fdf9f9f
SD_VAD	0x7ee00084	RO	32	0xffffffff	0000000000
SD_VIN	0x7ee00088	RW	32	0x9113ffff
SD_MR	0x7ee00090	RW	32	0xf0ffffff
SD_SD	0x7ee00094	RW	32	0xf1f71fff
SD_SE	0x7ee00098	RW	29	0x13f3f73f
SD_VER	0x7ee0009c	RO	32	0xffffffff	0x00000009
SD_STALL	0x7ee000a0	RW	10	0x000003ff
SD_REORD	0x7ee000a8	RO	28	0x0fffffff	0000000000
SD_LAC	0x7ee000ac	RO	28	0x0fffffff	0000000000
SD_PRE	0x7ee000b0	RO	28	0x0fffffff	0000000000
SD_SF	0x7ee000b4	RW	30	0x3fffffff
SD_CARCRC	0x7ee00100	RO	32	0xffffffff
SD_DMRCRC0	0x7ee00104	RO	32	0xffffffff
SD_DMRCRC1	0x7ee00108	RO	32	0xffffffff
SD_DQRCRC0	0x7ee0010c	RO	32	0xffffffff
SD_DQRCRC1	0x7ee00110	RO	32	0xffffffff
SD_DQRCRC2	0x7ee00114	RO	32	0xffffffff
SD_DQRCRC3	0x7ee00118	RO	32	0xffffffff
SD_DQRCRC4	0x7ee0011c	RO	32	0xffffffff
SD_DQRCRC5	0x7ee00120	RO	32	0xffffffff
SD_DQRCRC6	0x7ee00124	RO	32	0xffffffff
SD_DQRCRC7	0x7ee00128	RO	32	0xffffffff
SD_DQRCRC8	0x7ee0012c	RO	32	0xffffffff
SD_DQRCRC9	0x7ee00130	RO	32	0xffffffff
SD_DQRCRC10	0x7ee00134	RO	32	0xffffffff
SD_DQRCRC11	0x7ee00138	RO	32	0xffffffff
SD_DQRCRC12	0x7ee0013c	RO	32	0xffffffff
SD_DQRCRC13	0x7ee00140	RO	32	0xffffffff
SD_DQRCRC14	0x7ee00144	RO	32	0xffffffff
SD_DQRCRC15	0x7ee00148	RO	32	0xffffffff
SD_DQLCRC0	0x7ee0014c	RO	32	0xffffffff
SD_DQLCRC1	0x7ee00150	RO	32	0xffffffff
SD_DQLCRC2	0x7ee00154	RO	32	0xffffffff
SD_DQLCRC3	0x7ee00158	RO	32	0xffffffff
SD_DQLCRC4	0x7ee0015c	RO	32	0xffffffff
SD_DQLCRC5	0x7ee00160	RO	32	0xffffffff
SD_DQLCRC6	0x7ee00164	RO	32	0xffffffff
SD_DQLCRC7	0x7ee00168	RO	32	0xffffffff
SD_DQLCRC8	0x7ee0016c	RO	32	0xffffffff
SD_DQLCRC9	0x7ee00170	RO	32	0xffffffff
SD_DQLCRC10	0x7ee00174	RO	32	0xffffffff
SD_DQLCRC11	0x7ee00178	RO	32	0xffffffff
SD_DQLCRC12	0x7ee0017c	RO	32	0xffffffff
SD_DQLCRC13	0x7ee00180	RO	32	0xffffffff
SD_DQLCRC14	0x7ee00184	RO	32	0xffffffff
SD_DQLCRC15	0x7ee00188	RO	32	0xffffffff

Unsupported defines

define	value
SD_HOST_DMA	0xd0000

Register:SD_CS (0x7ee00000)

field_name	start_bit	end_bit	set	clear	reset
SD_CS_RESTRT	0	0	0x00000001	0xfffffffe	0x0
SD_CS_EN	1	1	0x00000002	0xfffffffd	0x0
SD_CS_DPD	2	2	0x00000004	0xfffffffb	0x0
SD_CS_STBY	3	3	0x00000008	0xfffffff7	0x0
SD_CS_PUSKIP	4	4	0x00000010	0xffffffef	0x0
SD_CS_SDTST	5	5	0x00000020	0xffffffdf	0x0
SD_CS_STATEN	6	6	0x00000040	0xffffffbf	0x0
SD_CS_STOP	7	7	0x00000080	0xffffff7f	0x0
SD_CS_SREF2RUN	8	8	0x00000100	0xfffffeff	0x0
SD_CS_IDLE	9	9	0x00000200	0xfffffdff	0x0
SD_CS_DLLCAL	10	11	0x00000c00	0xfffff3ff	0x0
missing definiton	12	13	NA	NA	NA
SD_CS_CLKOFF	14	14	0x00004000	0xffffbfff	0x1
SD_CS_SDUP	15	15	0x00008000	0xffff7fff	0x0
SD_CS_RDH_IDLE	16	16	0x00010000	0xfffeffff	0x0
SD_CS_ASHDNE	17	17	0x00020000	0xfffdffff	0x0
SD_CS_DEL_KEEP	18	18	0x00040000	0xfffbffff	0x0
SD_CS_ASHDN_T	19	22	0x00780000	0xff87ffff	0xf
SD_CS_EXCEPTION	23	23	0x00800000	0xff7fffff	0x0
SD_CS_STALLING	24	24	0x01000000	0xfeffffff	0x0

Register:SD_SA (0x7ee00004)

field_name	start_bit	end_bit	set	clear	reset
SD_SA_POWSAVE	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	6	NA	NA	NA
SD_SA_CLKSTOP	7	7	0x00000080	0xffffff7f	0x1
SD_SA_PGEHLDE	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	14	NA	NA	NA
SD_SA_PGEHLD_IDL	15	15	0x00008000	0xffff7fff	0x0
SD_SA_RFSH_T	16	31	0xffff0000	0x0000ffff	0x30c

Register:SD_SB (0x7ee00008)

field_name	start_bit	end_bit	set	clear	reset
SD_SB_COLBITS	0	1	0x00000003	0xfffffffc	0x1
SD_SB_ROWBITS	2	3	0x0000000c	0xfffffff3	0x1
SD_SB_EIGHTBANK	4	4	0x00000010	0xffffffef	0x0
SD_SB_BANKLOW	5	6	0x00000060	0xffffff9f	0x0
SD_SB_REORDER	7	7	0x00000080	0xffffff7f	0x0
SD_SB_INHIBIT_LA	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	19	NA	NA	NA
SD_SB_STBY_T	20	31	0xfff00000	0x000fffff	0x0

Register:SD_SC (0x7ee0000c)

field_name	start_bit	end_bit	set	clear	reset
SD_SC_WL	0	2	0x00000007	0xfffffff8	0x2
missing definiton	3	3	NA	NA	NA
SD_SC_T_WTR	4	6	0x00000070	0xffffff8f	0x3
missing definiton	7	7	NA	NA	NA
SD_SC_T_WR	8	11	0x00000f00	0xfffff0ff	0x6
missing definiton	12	19	NA	NA	NA
SD_SC_T_RRD	20	23	0x00f00000	0xff0fffff	0x4
SD_SC_T_RFC	24	30	0x7f000000	0x80ffffff	0x1e

Register:SD_PT2 (0x7ee00010)

field_name	start_bit	end_bit	set	clear	reset
SD_PT2_T_INIT5	0	15	0x0000ffff	0xffff0000	0xfa0

Register:SD_PT1 (0x7ee00014)

field_name	start_bit	end_bit	set	clear	reset
SD_PT1_T_INIT1	0	7	0x000000ff	0xffffff00	0x28
SD_PT1_T_INIT3	8	27	0x0fffff00	0xf00000ff	0x13880

Register:SD_SECSRT0 (0x7ee0003c)

field_name	start_bit	end_bit	set	clear	reset
SD_SECSRT0_EN	0	0	0x00000001	0xfffffffe	0x0
SD_SECSRT0_ADDR_LS	1	12	0x00001ffe	0xffffe001	0x0
SD_SECSRT0_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECEND0 (0x7ee00040)

field_name	start_bit	end_bit	set	clear	reset
SD_SECEND0_ADDR_LS	0	12	0x00001fff	0xffffe000	0xfff
SD_SECEND0_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECSRT1 (0x7ee00044)

field_name	start_bit	end_bit	set	clear	reset
SD_SECSRT1_EN	0	0	0x00000001	0xfffffffe	0x0
SD_SECSRT1_ADDR_LS	1	12	0x00001ffe	0xffffe001	0x0
SD_SECSRT1_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECEND1 (0x7ee00048)

field_name	start_bit	end_bit	set	clear	reset
SD_SECEND1_ADDR_LS	0	12	0x00001fff	0xffffe000	0xfff
SD_SECEND1_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECSRT2 (0x7ee0004c)

field_name	start_bit	end_bit	set	clear	reset
SD_SECSRT2_EN	0	0	0x00000001	0xfffffffe	0x0
SD_SECSRT2_ADDR_LS	1	12	0x00001ffe	0xffffe001	0x0
SD_SECSRT2_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECEND2 (0x7ee00050)

field_name	start_bit	end_bit	set	clear	reset
SD_SECEND2_ADDR_LS	0	12	0x00001fff	0xffffe000	0xfff
SD_SECEND2_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECSRT3 (0x7ee00054)

field_name	start_bit	end_bit	set	clear	reset
SD_SECSRT3_EN	0	0	0x00000001	0xfffffffe	0x0
SD_SECSRT3_ADDR_LS	1	12	0x00001ffe	0xffffe001	0x0
SD_SECSRT3_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_SECEND3 (0x7ee00058)

field_name	start_bit	end_bit	set	clear	reset
SD_SECEND3_ADDR_LS	0	12	0x00001fff	0xffffe000	0xfff
SD_SECEND3_ADDR_MS	13	31	0xffffe000	0x00001fff	0x0

Register:SD_PHYC (0x7ee00060)

field_name	start_bit	end_bit	set	clear	reset
SD_PHYC_PHYRST	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	3	NA	NA	NA
SD_PHYC_VREF_ENB	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	7	NA	NA	NA
SD_PHYC_BIST_MODE	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	11	NA	NA	NA
SD_PHYC_IOB_TMODE	12	12	0x00001000	0xffffefff	0x0
missing definiton	13	15	NA	NA	NA
SD_PHYC_MDLL_TMODE	16	16	0x00010000	0xfffeffff	0x0
missing definiton	17	19	NA	NA	NA
SD_PHYC_CRC_EN	20	20	0x00100000	0xffefffff	0x0
missing definiton	21	23	NA	NA	NA
SD_PHYC_CRC_CLR	24	24	0x01000000	0xfeffffff	0x0

Register:SD_MRT (0x7ee00064)

field_name	start_bit	end_bit	set	clear	reset
SD_MRT_T_MRW	0	8	0x000001ff	0xfffffe00	0x4

Register:SD_TMC (0x7ee0007c)

field_name	start_bit	end_bit	set	clear	reset
SD_TMC_TSTCLK	0	0	0x00000001	0xfffffffe	0x0
SD_TMC_TS	1	1	0x00000002	0xfffffffd	0x0
missing definiton	2	3	NA	NA	NA
SD_TMC_IPSEL	4	6	0x00000070	0xffffff8f	0x0
missing definiton	7	7	NA	NA	NA
SD_TMC_IPRD	8	15	0x0000ff00	0xffff00ff	0x0
SD_TMC_TSTPAT	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_RWC (0x7ee00080)

field_name	start_bit	end_bit	set	clear	reset
SD_RWC_RXVAL	0	4	0x0000001f	0xffffffe0	0x0
missing definiton	5	6	NA	NA	NA
SD_RWC_RXOVR	7	7	0x00000080	0xffffff7f	0x0
SD_RWC_WRTVAL	8	12	0x00001f00	0xffffe0ff	0x0
missing definiton	13	14	NA	NA	NA
SD_RWC_WRTOVR	15	15	0x00008000	0xffff7fff	0x0
SD_RWC_LASTCNT	16	20	0x001f0000	0xffe0ffff	0x0
missing definiton	21	21	NA	NA	NA
SD_RWC_MARGIN	22	23	0x00c00000	0xff3fffff	0x1
SD_RWC_MAXCNT	24	28	0x1f000000	0xe0ffffff	0x0
missing definiton	29	30	NA	NA	NA
SD_RWC_RSTMAX	31	31	0x80000000	0x7fffffff	0x0

Register:SD_VIN (0x7ee00088)

field_name	start_bit	end_bit	set	clear	reset
SD_VIN_ID	0	15	0x0000ffff	0xffff0000	0x0
SD_VIN_WRITE	16	16	0x00010000	0xfffeffff	0x0
SD_VIN_SPLIT	17	17	0x00020000	0xfffdffff	0x0
missing definiton	18	19	NA	NA	NA
SD_VIN_VIO	20	20	0x00100000	0xffefffff	0x0
missing definiton	21	23	NA	NA	NA
SD_VIN_MULT	24	24	0x01000000	0xfeffffff	0x0
missing definiton	25	27	NA	NA	NA
SD_VIN_INT_EN	28	28	0x10000000	0xefffffff	0x0
missing definiton	29	30	NA	NA	NA
SD_VIN_CLEAR	31	31	0x80000000	0x7fffffff	0x0

Register:SD_MR (0x7ee00090)

field_name	start_bit	end_bit	set	clear	reset
SD_MR_ADDR	0	7	0x000000ff	0xffffff00	0x0
SD_MR_WDATA	8	15	0x0000ff00	0xffff00ff	0x0
SD_MR_RDATA	16	23	0x00ff0000	0xff00ffff	0x0
missing definiton	24	27	NA	NA	NA
SD_MR_RW	28	28	0x10000000	0xefffffff	0x0
SD_MR_HI_Z	29	29	0x20000000	0xdfffffff	0x0
SD_MR_TIMEOUT	30	30	0x40000000	0xbfffffff	0x0
SD_MR_DONE	31	31	0x80000000	0x7fffffff	0x1

Register:SD_SD (0x7ee00094)

field_name	start_bit	end_bit	set	clear	reset
SD_SD_T_RCD	0	3	0x0000000f	0xfffffff0	0x8
SD_SD_T_RPpb	4	7	0x000000f0	0xffffff0f	0x8
SD_SD_T_RAS	8	12	0x00001f00	0xffffe0ff	0xe
missing definiton	13	15	NA	NA	NA
SD_SD_T_XP	16	18	0x00070000	0xfff8ffff	0x2
missing definiton	19	19	NA	NA	NA
SD_SD_T_RC	20	24	0x01f00000	0xfe0fffff	0x14
missing definiton	25	27	NA	NA	NA
SD_SD_T_RPab	28	31	0xf0000000	0x0fffffff	0xa

Register:SD_SE (0x7ee00098)

field_name	start_bit	end_bit	set	clear	reset
SD_SE_T_XSR	0	5	0x0000003f	0xffffffc0	0x28
missing definiton	6	7	NA	NA	NA
SD_SE_T_RTP	8	10	0x00000700	0xfffff8ff	0x3
missing definiton	11	11	NA	NA	NA
SD_SE_T_FAW	12	17	0x0003f000	0xfffc0fff	0x19
missing definiton	18	19	NA	NA	NA
SD_SE_RL	20	25	0x03f00000	0xfc0fffff	0x8
missing definiton	26	27	NA	NA	NA
SD_SE_RL_EN	28	28	0x10000000	0xefffffff	0x0

Register:SD_STALL (0x7ee000a0)

field_name	start_bit	end_bit	set	clear	reset
SD_STALL_CYCLES	0	9	0x000003ff	0xfffffc00	0x0

Register:SD_SF (0x7ee000b4)

field_name	start_bit	end_bit	set	clear	reset
SD_SF_MDLL_CAL	0	8	0x000001ff	0xfffffe00	0x12c
SD_SF_POWSAV_T	9	18	0x0007fe00	0xfff801ff	0x040
SD_SF_PGEHLD_T	19	28	0x1ff80000	0xe007ffff	0x100
SD_SF_PHYHOLD	29	29	0x20000000	0xdfffffff	0x0

Register:SD_CARCRC (0x7ee00100)

field_name	start_bit	end_bit	set	clear	reset
SD_CARCRC_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_CARCRC_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DMRCRC0 (0x7ee00104)

field_name	start_bit	end_bit	set	clear	reset
SD_DMRCRC0_LOW	0	15	0x0000ffff	0xffff0000	0x0
SD_DMRCRC0_HIGH	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DMRCRC1 (0x7ee00108)

field_name	start_bit	end_bit	set	clear	reset
SD_DMRCRC1_LOW	0	15	0x0000ffff	0xffff0000	0x0
SD_DMRCRC1_HIGH	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC0 (0x7ee0010c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC0_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC0_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC1 (0x7ee00110)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC1_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC1_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC2 (0x7ee00114)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC2_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC2_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC3 (0x7ee00118)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC3_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC3_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC4 (0x7ee0011c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC4_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC4_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC5 (0x7ee00120)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC5_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC5_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC6 (0x7ee00124)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC6_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC6_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC7 (0x7ee00128)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC7_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC7_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC8 (0x7ee0012c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC8_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC8_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC9 (0x7ee00130)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC9_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC9_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC10 (0x7ee00134)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC10_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC10_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC11 (0x7ee00138)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC11_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC11_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC12 (0x7ee0013c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC12_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC12_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC13 (0x7ee00140)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC13_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC13_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC14 (0x7ee00144)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC14_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC14_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQRCRC15 (0x7ee00148)

field_name	start_bit	end_bit	set	clear	reset
SD_DQRCRC15_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQRCRC15_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC0 (0x7ee0014c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC0_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC0_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC1 (0x7ee00150)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC1_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC1_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC2 (0x7ee00154)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC2_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC2_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC3 (0x7ee00158)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC3_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC3_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC4 (0x7ee0015c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC4_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC4_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC5 (0x7ee00160)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC5_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC5_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC6 (0x7ee00164)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC6_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC6_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC7 (0x7ee00168)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC7_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC7_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC8 (0x7ee0016c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC8_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC8_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC9 (0x7ee00170)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC9_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC9_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC10 (0x7ee00174)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC10_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC10_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC11 (0x7ee00178)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC11_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC11_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC12 (0x7ee0017c)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC12_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC12_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC13 (0x7ee00180)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC13_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC13_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC14 (0x7ee00184)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC14_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC14_RISE	16	31	0xffff0000	0x0000ffff	0x0

Register:SD_DQLCRC15 (0x7ee00188)

field_name	start_bit	end_bit	set	clear	reset
SD_DQLCRC15_FALL	0	15	0x0000ffff	0xffff0000	0x0
SD_DQLCRC15_RISE	16	31	0xffff0000	0x0000ffff	0x0

SH

Info

base	0x7e202000

Registers

register name	address	type	width	mask	reset
SH_CMD	0x7e202000	RW	16	0x0000cfff	0000000000
SH_ARG	0x7e202004	RW	32	0xffffffff	0000000000
SH_TOUT	0x7e202008	RW	32	0xffffffff	0x00a00000
SH_CDIV	0x7e20200c	RW	11	0x000007ff	0x000001fb
SH_RSP0	0x7e202010	RO	32	0xffffffff
SH_RSP1	0x7e202014	RO	32	0xffffffff	0000000000
SH_RSP2	0x7e202018	RO	32	0xffffffff	0000000000
SH_RSP3	0x7e20201c	RO	32	0xffffffff	0000000000
SH_HSTS	0x7e202020	RW	11	0x000007f9	0000000000
SH_VDD	0x7e202030	RW	1	0x00000001	0000000000
SH_EDM	0x7e202034	RW	19	0x0007ffff
SH_HCFG	0x7e202038	RW	11	0x0000073f	0000000000
SH_HBCT	0x7e20203c	RW	32	0xffffffff	0x00000400
SH_DATA	0x7e202040	RW	32	0xffffffff
SH_HBLC	0x7e202050	RW	16	0x0000ffff	0000000000

Register:SH_CMD (0x7e202000)

field_name	start_bit	end_bit	set	clear	reset
SH_CMD_COMMAND	0	5	0x0000003f	0xffffffc0	0x0
SH_CMD_READ_CMD	6	6	0x00000040	0xffffffbf	0x0
SH_CMD_WRITE_CMD	7	8	0x00000180	0xfffffe7f	0x0
SH_CMD_LONG_RESPONSE	9	9	0x00000200	0xfffffdff	0x0
SH_CMD_NO_RESPONSE	10	10	0x00000400	0xfffffbff	0x0
SH_CMD_BUSY_CMD	11	11	0x00000800	0xfffff7ff	0x0
missing definiton	12	13	NA	NA	NA
SH_CMD_FAIL_FLAG	14	14	0x00004000	0xffffbfff	0x0
SH_CMD_NEW_FLAG	15	15	0x00008000	0xffff7fff	0x0

Register:SH_ARG (0x7e202004)

field_name	start_bit	end_bit	set	clear	reset
SH_ARG_ARGUMENT	0	31	0xffffffff	0x00000000	0x0

Register:SH_TOUT (0x7e202008)

field_name	start_bit	end_bit	set	clear	reset
SH_TOUT_TIME_OUT	0	31	0xffffffff	0x00000000	0xa00000

Register:SH_CDIV (0x7e20200c)

field_name	start_bit	end_bit	set	clear	reset
SH_CDIV_CLOCKDIV	0	10	0x000007ff	0xfffff800	0x1fb

Register:SH_RSP0 (0x7e202010)

field_name	start_bit	end_bit	set	clear	reset
SH_RSP0_CARD_STATUS	0	31	0xffffffff	0x00000000

Register:SH_RSP1 (0x7e202014)

field_name	start_bit	end_bit	set	clear	reset
SH_RSP1_CID_CSD	0	31	0xffffffff	0x00000000	0x0

Register:SH_RSP2 (0x7e202018)

field_name	start_bit	end_bit	set	clear	reset
SH_RSP2_CID_CSD	0	31	0xffffffff	0x00000000	0x0

Register:SH_RSP3 (0x7e20201c)

field_name	start_bit	end_bit	set	clear	reset
SH_RSP3_CID_CSD	0	31	0xffffffff	0x00000000	0x0

Register:SH_HSTS (0x7e202020)

field_name	start_bit	end_bit	set	clear	reset
SH_HSTS_DATA_FLAG	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	2	NA	NA	NA
SH_HSTS_FIFO_ERROR	3	3	0x00000008	0xfffffff7	0x0
SH_HSTS_CRC7_ERROR	4	4	0x00000010	0xffffffef	0x0
SH_HSTS_CRC16_ERROR	5	5	0x00000020	0xffffffdf	0x0
SH_HSTS_CMD_TIME_OUT	6	6	0x00000040	0xffffffbf	0x0
SH_HSTS_REW_TIME_OUT	7	7	0x00000080	0xffffff7f	0x0
SH_HSTS_SDIO_IRPT	8	8	0x00000100	0xfffffeff	0x0
SH_HSTS_BLOCK_IRPT	9	9	0x00000200	0xfffffdff	0x0
SH_HSTS_BUSY_IRPT	10	10	0x00000400	0xfffffbff	0x0

Register:SH_VDD (0x7e202030)

field_name	start_bit	end_bit	set	clear	reset
SH_VDD_POWER_ON	0	0	0x00000001	0xfffffffe	0x0

Register:SH_EDM (0x7e202034)

field_name	start_bit	end_bit	set	clear
SH_EDM_STATE_MACHINE	0	3	0x0000000f	0xfffffff0
SH_EDM_FIFO_COUNT	4	8	0x000001f0	0xfffffe0f
SH_EDM_WRITE_THRESHOLD	9	13	0x00003e00	0xffffc1ff
SH_EDM_READ_THRESHOLD	14	18	0x0007c000	0xfff83fff

Register:SH_HCFG (0x7e202038)

field_name	start_bit	end_bit	set	clear	reset
SH_HCFG_REL_CMD_LINE	0	0	0x00000001	0xfffffffe	0x0
SH_HCFG_WIDE_INT_BUS	1	1	0x00000002	0xfffffffd	0x0
SH_HCFG_WIDE_EXT_BUS	2	2	0x00000004	0xfffffffb	0x0
SH_HCFG_SLOW_CARD	3	3	0x00000008	0xfffffff7	0x0
SH_HCFG_DATA_IRPT_EN	4	4	0x00000010	0xffffffef	0x0
SH_HCFG_SDIO_IRPT_EN	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	7	NA	NA	NA
SH_HCFG_BLOCK_IRPT_EN	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	9	NA	NA	NA
SH_HCFG_BUSY_IRPT_EN	10	10	0x00000400	0xfffffbff	0x0

Register:SH_HBCT (0x7e20203c)

field_name	start_bit	end_bit	set	clear	reset
SH_HBCT_BYTECOUNT	0	31	0xffffffff	0x00000000	0x400

Register:SH_DATA (0x7e202040)

field_name	start_bit	end_bit	set	clear	reset
SH_DATA_DATA	0	31	0xffffffff	0x00000000

Register:SH_HBLC (0x7e202050)

field_name	start_bit	end_bit	set	clear	reset
SH_HBLC_BLOCKCOUNT	0	8	0x000001ff	0xfffffe00	0x0

SLIM

Info

base	0x7e210000
id	0x736c696d

Registers

register name	address	type	width	mask	reset
SLIM_CON	0x7e210000	RW	32	0xfffff0ff	0x000000c1
SLIM_CON2	0x7e210004	RW	32	0xff008001	0000000000
SLIM_STAT	0x7e210008	RW	26	0x03ffffff	0000000000
SLIM_FS	0x7e21000c	RW	14	0x00003fff	0000000000
SLIM_EA0	0x7e210010	RW	32	0xffff00ff	0000000000
SLIM_EA1	0x7e210014	RW	32	0x8000ffff	0000000000
SLIM_DMA_MC_RX	0x7e210020	RW	32	0xffffffff	0000000000
SLIM_DMA_MC_TX	0x7e210024	RW	32	0xffffffff	0000000000
SLIM_DMA_DC0	0x7e210030	RW	32	0xffffffff	0000000000
SLIM_DMA_DC1	0x7e210034	RW	32	0xffffffff	0000000000
SLIM_DMA_DC2	0x7e210038	RW	32	0xffffffff	0000000000
SLIM_DMA_DC3	0x7e21003c	RW	32	0xffffffff	0000000000
SLIM_DMA_DC4	0x7e210040	RW	32	0xffffffff	0000000000
SLIM_DMA_DC5	0x7e210044	RW	32	0xffffffff	0000000000
SLIM_DMA_DC6	0x7e210048	RW	32	0xffffffff	0000000000
SLIM_DMA_DC7	0x7e21004c	RW	32	0xffffffff	0000000000
SLIM_DMA_DC8	0x7e210050	RW	32	0xffffffff	0000000000
SLIM_DMA_DC9	0x7e210054	RW	32	0xffffffff	0000000000
SLIM_DMA_MC_CON	0x7e210080	RW	2	0x00000003	0000000000
SLIM_DMA_DC_CON	0x7e210084	RW	20	0x000fffff	0000000000
SLIM_DMA_MC_STAT	0x7e210088	RW	4	0x0000000f	0000000000
SLIM_DMA_DC_STAT_0	0x7e21008c	RW	32	0xffffffff	0000000000
SLIM_DMA_DC_STAT_1	0x7e210090	RW	20	0x000f000f	0000000000
SLIM_MC_IN_CON	0x7e210100	RW	12	0x00000f1d	0000000000
SLIM_MC_IN_STAT	0x7e210104	RW	4	0x0000000f	0000000000
SLIM_MC_OUT_CON	0x7e210120	RW	7	0x00000048	0000000000
SLIM_MC_OUT_STAT	0x7e210124	RW	4	0x00000008	0000000000
SLIM_DCC0_PA0	0x7e210200	RW	24	0x00ffff1f	0000000000
SLIM_DCC0_PA1	0x7e210204	RW	24	0x00ffff3f	0000000000
SLIM_DCC0_CON	0x7e210208	RW	32	0xffff0070	0000000000
SLIM_DCC0_STAT	0x7e21020c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC0_PROT	0x7e210210	RW	32	0xc001ffff	0x000093a0
SLIM_DCC1_PA0	0x7e210220	RW	24	0x00ffff1f	0000000000
SLIM_DCC1_PA1	0x7e210224	RW	24	0x00ffff3f	0000000000
SLIM_DCC1_CON	0x7e210228	RW	32	0xffff0070	0000000000
SLIM_DCC1_STAT	0x7e21022c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC1_PROT	0x7e210230	RW	32	0xc001ffff	0x000093a0
SLIM_DCC2_PA0	0x7e210240	RW	24	0x00ffff1f	0000000000
SLIM_DCC2_PA1	0x7e210244	RW	24	0x00ffff3f	0000000000
SLIM_DCC2_CON	0x7e210248	RW	32	0xffff0070	0000000000
SLIM_DCC2_STAT	0x7e21024c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC2_PROT	0x7e210250	RW	32	0xc001ffff	0x000093a0
SLIM_DCC3_PA0	0x7e210260	RW	24	0x00ffff1f	0000000000
SLIM_DCC3_PA1	0x7e210264	RW	24	0x00ffff3f	0000000000
SLIM_DCC3_CON	0x7e210268	RW	32	0xffff0070	0000000000
SLIM_DCC3_STAT	0x7e21026c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC3_PROT	0x7e210270	RW	32	0xc001ffff	0x000093a0
SLIM_DCC4_PA0	0x7e210280	RW	24	0x00ffff1f	0000000000
SLIM_DCC4_PA1	0x7e210284	RW	24	0x00ffff3f	0000000000
SLIM_DCC4_CON	0x7e210288	RW	32	0xffff0070	0000000000
SLIM_DCC4_STAT	0x7e21028c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC4_PROT	0x7e210290	RW	32	0xc001ffff	0x000093a0
SLIM_DCC5_PA0	0x7e2102a0	RW	24	0x00ffff1f	0000000000
SLIM_DCC5_PA1	0x7e2102a4	RW	24	0x00ffff3f	0000000000
SLIM_DCC5_CON	0x7e2102a8	RW	32	0xffff0070	0000000000
SLIM_DCC5_STAT	0x7e2102ac	RW	32	0xc0ff00c7	0000000000
SLIM_DCC5_PROT	0x7e2102b0	RW	32	0xc001ffff	0x000093a0
SLIM_DCC6_PA0	0x7e2102c0	RW	24	0x00ffff1f	0000000000
SLIM_DCC6_PA1	0x7e2102c4	RW	24	0x00ffff3f	0000000000
SLIM_DCC6_CON	0x7e2102c8	RW	32	0xffff0070	0000000000
SLIM_DCC6_STAT	0x7e2102cc	RW	32	0xc0ff00c7	0000000000
SLIM_DCC6_PROT	0x7e2102d0	RW	32	0xc001ffff	0x000093a0
SLIM_DCC7_PA0	0x7e2102e0	RW	24	0x00ffff1f	0000000000
SLIM_DCC7_PA1	0x7e2102e4	RW	24	0x00ffff3f	0000000000
SLIM_DCC7_CON	0x7e2102e8	RW	32	0xffff0070	0000000000
SLIM_DCC7_STAT	0x7e2102ec	RW	32	0xc0ff00c7	0000000000
SLIM_DCC7_PROT	0x7e2102f0	RW	32	0xc001ffff	0x000093a0
SLIM_DCC8_PA0	0x7e210300	RW	24	0x00ffff1f	0000000000
SLIM_DCC8_PA1	0x7e210304	RW	24	0x00ffff3f	0000000000
SLIM_DCC8_CON	0x7e210308	RW	32	0xffff0070	0000000000
SLIM_DCC8_STAT	0x7e21030c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC8_PROT	0x7e210310	RW	32	0xc001ffff	0x000093a0
SLIM_DCC9_PA0	0x7e210320	RW	24	0x00ffff1f	0000000000
SLIM_DCC9_PA1	0x7e210324	RW	24	0x00ffff3f	0000000000
SLIM_DCC9_CON	0x7e210328	RW	32	0xffff0070	0000000000
SLIM_DCC9_STAT	0x7e21032c	RW	32	0xc0ff00c7	0000000000
SLIM_DCC9_PROT	0x7e210330	RW	32	0xc001ffff	0x000093a0

Unsupported defines

define	value
SLIM_CRX_DMA	0xb0000
SLIM_CTX_DMA	0xa0000
SLIM_DCC_BASE(n)	MACRO
SLIM_DCC_CON(n)	MACRO
SLIM_DCC_PA0(n)	MACRO
SLIM_DCC_PA1(n)	MACRO
SLIM_DCC_STAT(n)	MACRO
SLIM_DRX_DMA	0x90000
SLIM_DTX_DMA	0x80000
SLIM_NUM_DCC	10

SMI

Info

base	0x7e600000
id	0x534d4958

Registers

register name	address	type	width	mask	reset
SMI_CS	0x7e600000	RW	32	0xff00ffff
SMI_L	0x7e600004	RW	32	0xffffffff	0000000000
SMI_A	0x7e600008	RW	10	0x0000033f	0000000000
SMI_D	0x7e60000c	RW	32	0xffffffff	0000000000
SMI_DSR0	0x7e600010	RW	32	0xffffffff	0x0101000c
SMI_DSW0	0x7e600014	RW	32	0xffffffff	0x0101000c
SMI_DSR1	0x7e600018	RW	32	0xffffffff	0x0101000c
SMI_DSW1	0x7e60001c	RW	32	0xffffffff	0x0101000c
SMI_DSR2	0x7e600020	RW	32	0xffffffff	0x0101000c
SMI_DSW2	0x7e600024	RW	32	0xffffffff	0x0101000c
SMI_DSR3	0x7e600028	RW	32	0xffffffff	0x0101000c
SMI_DSW3	0x7e60002c	RW	32	0xffffffff	0x0101000c
SMI_DC	0x7e600030	RW	29	0x11ffffff	0x00c10820
SMI_DCS	0x7e600034	RW	4	0x0000000f	0000000000
SMI_DA	0x7e600038	RW	10	0x0000033f	0000000000
SMI_DD	0x7e60003c	RW	18	0x0003ffff	0000000000
SMI_FD	0x7e600040	RW	14	0x00003f3f	0000000000

Unsupported defines

define	value
SMI_BASE_DIRECT	0x7E601000
SMI_DMA	0x40000
SMI_FIFO_ADDRESS(device,addr)	MACRO
SMI_SCALER_0_DMA	0x180000
SMI_SCALER_1_DMA	0x190000
SMI_SCALER_2_DMA	0x1a0000

Register:SMI_CS (0x7e600000)

field_name	start_bit	end_bit	set	clear	reset
SMI_CS_ENABLE	0	0	0x00000001	0xfffffffe	0x0
SMI_CS_DONE	1	1	0x00000002	0xfffffffd	0x0
SMI_CS_ACTIVE	2	2	0x00000004	0xfffffffb	0x0
SMI_CS_START	3	3	0x00000008	0xfffffff7	0x0
SMI_CS_CLEAR	4	4	0x00000010	0xffffffef	0x0
SMI_CS_WRITE	5	5	0x00000020	0xffffffdf	0x0
SMI_CS_PAD	6	7	0x000000c0	0xffffff3f	0x0
SMI_CS_TEEN	8	8	0x00000100	0xfffffeff	0x0
SMI_CS_INTD	9	9	0x00000200	0xfffffdff	0x0
SMI_CS_INTT	10	10	0x00000400	0xfffffbff	0x0
SMI_CS_INTR	11	11	0x00000800	0xfffff7ff	0x0
SMI_CS_PVMODE	12	12	0x00001000	0xffffefff	0x0
SMI_CS_SETERR	13	13	0x00002000	0xffffdfff	0x0
SMI_CS_PXLDAT	14	14	0x00004000	0xffffbfff	0x0
SMI_CS_EDREQ	15	15	0x00008000	0xffff7fff	0x0
missing definiton	16	23	NA	NA	NA
SMI_CS_PRDY	24	24	0x01000000	0xfeffffff	0x0
SMI_CS_AFERR	25	25	0x02000000	0xfdffffff	0x0
SMI_CS_TXW	26	26	0x04000000	0xfbffffff	0x1
SMI_CS_RXR	27	27	0x08000000	0xf7ffffff	0x0
SMI_CS_TXD	28	28	0x10000000	0xefffffff	0x1
SMI_CS_RXD	29	29	0x20000000	0xdfffffff	0x0
SMI_CS_TXE	30	30	0x40000000	0xbfffffff	0x1
SMI_CS_RXF	31	31	0x80000000	0x7fffffff	0x0

Register:SMI_A (0x7e600008)

field_name	start_bit	end_bit	set	clear	reset
SMI_A_ADDR	0	5	0x0000003f	0xffffffc0	0x0
missing definiton	6	7	NA	NA	NA
SMI_A_DEVICE	8	9	0x00000300	0xfffffcff	0x0

Register:SMI_DSR0 (0x7e600010)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSR0_RSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSR0_RDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSR0_RPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSR0_RPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSR0_RHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSR0_FSETUP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSR0_MODE68	23	23	0x00800000	0xff7fffff	0x0
SMI_DSR0_RSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSR0_RWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSW0 (0x7e600014)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSW0_WSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSW0_WDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSW0_WPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSW0_WPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSW0_WHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSW0_WSWAP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSW0_WFORMAT	23	23	0x00800000	0xff7fffff	0x0
SMI_DSW0_WSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSW0_WWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSR1 (0x7e600018)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSR1_RSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSR1_RDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSR1_RPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSR1_RPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSR1_RHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSR1_FSETUP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSR1_MODE68	23	23	0x00800000	0xff7fffff	0x0
SMI_DSR1_RSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSR1_RWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSW1 (0x7e60001c)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSW1_WSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSW1_WDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSW1_WPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSW1_WPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSW1_WHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSW1_WSWAP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSW1_WFORMAT	23	23	0x00800000	0xff7fffff	0x0
SMI_DSW1_WSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSW1_WWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSR2 (0x7e600020)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSR2_RSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSR2_RDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSR2_RPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSR2_RPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSR2_RHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSR2_FSETUP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSR2_MODE68	23	23	0x00800000	0xff7fffff	0x0
SMI_DSR2_RSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSR2_RWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSW2 (0x7e600024)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSW2_WSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSW2_WDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSW2_WPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSW2_WPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSW2_WHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSW2_WSWAP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSW2_WFORMAT	23	23	0x00800000	0xff7fffff	0x0
SMI_DSW2_WSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSW2_WWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSR3 (0x7e600028)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSR3_RSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSR3_RDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSR3_RPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSR3_RPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSR3_RHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSR3_FSETUP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSR3_MODE68	23	23	0x00800000	0xff7fffff	0x0
SMI_DSR3_RSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSR3_RWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DSW3 (0x7e60002c)

field_name	start_bit	end_bit	set	clear	reset
SMI_DSW3_WSTROBE	0	6	0x0000007f	0xffffff80	0xc
SMI_DSW3_WDREQ	7	7	0x00000080	0xffffff7f	0x0
SMI_DSW3_WPACE	8	14	0x00007f00	0xffff80ff	0x0
SMI_DSW3_WPACEALL	15	15	0x00008000	0xffff7fff	0x0
SMI_DSW3_WHOLD	16	21	0x003f0000	0xffc0ffff	0x1
SMI_DSW3_WSWAP	22	22	0x00400000	0xffbfffff	0x0
SMI_DSW3_WFORMAT	23	23	0x00800000	0xff7fffff	0x0
SMI_DSW3_WSETUP	24	29	0x3f000000	0xc0ffffff	0x1
SMI_DSW3_WWIDTH	30	31	0xc0000000	0x3fffffff	0x0

Register:SMI_DC (0x7e600030)

field_name	start_bit	end_bit	set	clear	reset
SMI_DC_REQW	0	5	0x0000003f	0xffffffc0	0x20
SMI_DC_REQR	6	11	0x00000fc0	0xfffff03f	0x20
SMI_DC_PANICW	12	17	0x0003f000	0xfffc0fff	0x10
SMI_DC_PANICR	18	23	0x00fc0000	0xff03ffff	0x30
SMI_DC_DMAP	24	24	0x01000000	0xfeffffff	0x0
missing definiton	25	27	NA	NA	NA
SMI_DC_DMAEN	28	28	0x10000000	0xefffffff	0x0

Register:SMI_DCS (0x7e600034)

field_name	start_bit	end_bit	set	clear	reset
SMI_DCS_EANBLE	0	0	0x00000001	0xfffffffe	0x0
SMI_DCS_START	1	1	0x00000002	0xfffffffd	0x0
SMI_DCS_DONE	2	2	0x00000004	0xfffffffb	0x0
SMI_DCS_WRITE	3	3	0x00000008	0xfffffff7	0x0

Register:SMI_DA (0x7e600038)

field_name	start_bit	end_bit	set	clear	reset
SMI_DA_ADDR	0	5	0x0000003f	0xffffffc0	0x0
missing definiton	6	7	NA	NA	NA
SMI_DA_WRITE	8	9	0x00000300	0xfffffcff	0x0

Register:SMI_FD (0x7e600040)

field_name	start_bit	end_bit	set	clear	reset
SMI_FD_FCNT	0	5	0x0000003f	0xffffffc0	0x0
missing definiton	6	7	NA	NA	NA
SMI_FD_FLVL	8	13	0x00003f00	0xffffc0ff	0x0

SPI

Info

base	0x7e204000

Registers

register name	address	type	width	mask	reset
SPI_CS	0x7e204000	RW	21	0x001f07ff	0000000000
SPI_FIFO	0x7e204004	RW	8	0x000000ff	0000000000
SPI_CLK	0x7e204008	RW	16	0x0000ffff	0000000000
SPI_DLEN	0x7e20400c	RW	16	0x0000ffff	0000000000
SPI_LTOH	0x7e204010	RW	4	0x0000000f	0x00000001

Unsupported defines

define	value
SPI_RX_DMA	0x70000
SPI_TX_DMA	0x60000

Register:SPI_CS (0x7e204000)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	1	NA	NA	NA
SPI_CS_CPHA	2	2	0x00000004	0xfffffffb	0x0
SPI_CS_CPOL	3	3	0x00000008	0xfffffff7	0x0
SPI_CS_CLEAR	4	5	0x00000030	0xffffffcf	0x0
SPI_CS_CSPOL	6	6	0x00000040	0xffffffbf	0x0
SPI_CS_TA	7	7	0x00000080	0xffffff7f	0x0
SPI_CS_DMAEN	8	8	0x00000100	0xfffffeff	0x0
SPI_CS_INTD	9	9	0x00000200	0xfffffdff	0x0
SPI_CS_INTR	10	10	0x00000400	0xfffffbff	0x0
missing definiton	11	15	NA	NA	NA
SPI_CS_DONE	16	16	0x00010000	0xfffeffff	0x0
SPI_CS_RXD	17	17	0x00020000	0xfffdffff	0x0
SPI_CS_TXD	18	18	0x00040000	0xfffbffff	0x0
SPI_CS_RXR	19	19	0x00080000	0xfff7ffff	0x0
SPI_CS_RXF	20	20	0x00100000	0xffefffff	0x0

Register:SPI_FIFO (0x7e204004)

field_name	start_bit	end_bit	set	clear	reset
SPI_FIFO_DATA	0	7	0x000000ff	0xffffff00	0x0

Register:SPI_CLK (0x7e204008)

field_name	start_bit	end_bit	set	clear	reset
SPI_CLK_CDIV	0	15	0x0000ffff	0xffff0000	0x0

Register:SPI_DLEN (0x7e20400c)

field_name	start_bit	end_bit	set	clear	reset
SPI_DLEN_LEN	0	15	0x0000ffff	0xffff0000	0x0

Register:SPI_LTOH (0x7e204010)

field_name	start_bit	end_bit	set	clear	reset
SPI_LTOH_TOH	0	3	0x0000000f	0xfffffff0	0x1

ST

Info

base	0x7e003000

Registers

register name	address	type	width	mask	reset
ST_CS	0x7e003000	RW	32	0xffffffff	0000000000
ST_CLO	0x7e003004	RO	32	0xffffffff
ST_CHI	0x7e003008	RO	32	0xffffffff
ST_C0	0x7e00300c	RW	32	0xffffffff	0000000000
ST_C1	0x7e003010	RW	32	0xffffffff	0000000000
ST_C2	0x7e003014	RW	32	0xffffffff	0000000000
ST_C3	0x7e003018	RW	32	0xffffffff	0000000000

SYSAC

Info

base	0x7e009000
id	0x4152424d

Registers

register name	address	type	width	mask
SYSAC_HOST_PRIORITY	0x7e009000	RW	4	0x0000000f
SYSAC_DBG_PRIORITY	0x7e009004	RW	4	0x0000000f
SYSAC_HVSM_PRIORITY	0x7e009008	RW	8	0x000000ff
SYSAC_V3D_PRIORITY	0x7e00900c	RW	4	0x0000000f
SYSAC_H264_PRIORITY	0x7e009010	RW	4	0x0000000f
SYSAC_JPEG_PRIORITY	0x7e009014	RW	8	0x000000ff
SYSAC_TRANS_PRIORITY	0x7e009018	RW	8	0x000000ff
SYSAC_ISP_PRIORITY	0x7e00901c	RW	4	0x0000000f
SYSAC_USB_PRIORITY	0x7e009020	RW	4	0x0000000f
SYSAC_L2_ARBITER_CONTROL	0x7e009040	RW	16	0x0000ffff
SYSAC_UC_ARBITER_CONTROL	0x7e009044	RW	16	0x0000ffff
SYSAC_SRC_ARBITER_CONTROL	0x7e009048	RW	16	0x0000ffff
SYSAC_PERI_ARBITER_CONTROL	0x7e00904c	RW	16	0x0000ffff
SYSAC_DMA_ARBITER_CONTROL_UC	0x7e009050	RW	16	0x0000ffff
SYSAC_DMA_ARBITER_CONTROL_L2	0x7e009054	RW	16	0x0000ffff
SYSAC_DMA_ARBITER_CONTROL_PER	0x7e009058	RW	16	0x0000ffff
SYSAC_DMA_ARBITER_CONTROL_LITE	0x7e00905c	RW	16	0x0000ffff
SYSAC_DUMMY_STATUS	0x7e009060	RW	1	0x00000001
SYSAC_DMA_DREQ_CONTROL	0x7e009064	RW	4	0x0000000f
SYSAC_V3D_LIMITER	0x7e009068	RW	12	0x00000fff

Unsupported defines

define	value
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0

Register:SYSAC_HOST_PRIORITY (0x7e009000)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_HOST_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_DBG_PRIORITY (0x7e009004)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DBG_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_HVSM_PRIORITY (0x7e009008)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_HVSM_PRIORITY_N_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0
SYSAC_HVSM_PRIORITY_P_PRIORITY	4	7	0x000000f0	0xffffff0f	0x0

Register:SYSAC_V3D_PRIORITY (0x7e00900c)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_V3D_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_H264_PRIORITY (0x7e009010)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_H264_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_JPEG_PRIORITY (0x7e009014)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_JPEG_PRIORITY_N_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0
SYSAC_JPEG_PRIORITY_P_PRIORITY	4	7	0x000000f0	0xffffff0f	0x0

Register:SYSAC_TRANS_PRIORITY (0x7e009018)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_TRANS_PRIORITY_N_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0
SYSAC_TRANS_PRIORITY_P_PRIORITY	4	7	0x000000f0	0xffffff0f	0x0

Register:SYSAC_ISP_PRIORITY (0x7e00901c)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_ISP_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_USB_PRIORITY (0x7e009020)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_USB_PRIORITY_PRIORITY	0	3	0x0000000f	0xfffffff0	0x0

Register:SYSAC_L2_ARBITER_CONTROL (0x7e009040)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_L2_ARBITER_CONTROL_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_L2_ARBITER_CONTROL_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_L2_ARBITER_CONTROL_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_L2_ARBITER_CONTROL_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_UC_ARBITER_CONTROL (0x7e009044)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_UC_ARBITER_CONTROL_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_UC_ARBITER_CONTROL_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_UC_ARBITER_CONTROL_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_UC_ARBITER_CONTROL_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_SRC_ARBITER_CONTROL (0x7e009048)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_SRC_ARBITER_CONTROL_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_SRC_ARBITER_CONTROL_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_PERI_ARBITER_CONTROL (0x7e00904c)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_PERI_ARBITER_CONTROL_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_PERI_ARBITER_CONTROL_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_DMA_ARBITER_CONTROL_UC (0x7e009050)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_DMA_ARBITER_CONTROL_L2 (0x7e009054)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0

Register:SYSAC_DMA_ARBITER_CONTROL_PER (0x7e009058)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_DMA_ARBITER_CONTROL_LITE (0x7e00905c)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT	0	1	0x00000003	0xfffffffc	0x0
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY	2	3	0x0000000c	0xfffffff3	0x0
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:SYSAC_DUMMY_STATUS (0x7e009060)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DUMMY_STATUS_IDLE	0	0	0x00000001	0xfffffffe	0x0

Register:SYSAC_DMA_DREQ_CONTROL (0x7e009064)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE	0	2	0x00000007	0xfffffff8	0x0
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR	3	3	0x00000008	0xfffffff7	0x0

Register:SYSAC_V3D_LIMITER (0x7e009068)

field_name	start_bit	end_bit	set	clear	reset
SYSAC_V3D_LIMITER_HOLDOFF	0	0	0x00000001	0xfffffffe	0x0
SYSAC_V3D_LIMITER_INCREMENT	0	0	0x00000001	0xfffffffe	0x0
SYSAC_V3D_LIMITER_ENABLE	0	0	0x00000001	0xfffffffe	0x0
missing definiton	1	-1	NA	NA	NA
SYSAC_V3D_LIMITER_SPARE	1	3	0x0000000e	0xfffffff1	0x0
SYSAC_V3D_LIMITER_MAX_PRIORITY	3	7	0x000000f8	0xffffff07	0x0
missing definiton	4	2	NA	NA	NA

TB

Info

base	0x7e20b000

Registers

register name	address	type	width	mask
TB_TASK	0x7e20b000	RW	17	0x0001ffff
TB_ADDR	0x7e20b000	RW	32	0xffffffff
TB_TASK_PARAM1	0x7e20b004	RW	32	0xffffffff
TB_TASK_PARAM2	0x7e20b008	RW	32	0xffffffff
TB_TASK_PARAM3	0x7e20b00c	RW	32	0xffffffff
TB_TASK_STATUS	0x7e20b080	RW	32	0xffffffff
TB_TASK_RXDATA1	0x7e20b084	RW	32	0xffffffff
TB_TASK_RXDATA2	0x7e20b088	RW	32	0xffffffff
TB_TASK_TXTCLR	0x7e20b0f0	RW	32	0xffffffff
TB_HDMI	0x7e20b100	RW	32	0xffffffff
TB_PCM	0x7e20b200	RW	32	0xffffffff
TB_HOST	0x7e20b300	RW	32	0xffffffff
TB_PRINTER_CTRL	0x7e20b400	RW	16	0x0000fff3
TB_PRINTER_DATA	0x7e20b404	RW	32	0xffffffff
TB_BOOT_ADDR	0x7e20b500	RW	32	0xffffffff
TB_BOOT_OPT	0x7e20b504	RW	32	0x800007ff
TB_BOOT_SECURE_MODE	0x7e20b508	RW	2	0x00000003
TB_BOOT_STATUS	0x7e20b50c	RW	1	0x00000001
TB_JTB_CONFIG	0x7e20b800	RW	32	0xbfffffff
TB_JTB_TMS	0x7e20b804	RW	32	0xffffffff
TB_JTB_TDI	0x7e20b808	RW	32	0xffffffff
TB_JTB_TDO	0x7e20b80c	RO	32	0xffffffff
TB_JTB_BITCNT	0x7e20b810	RW	6	0x0000003f
TB_JTB_PORTEN	0x7e20b814	RW	8	0x000000ff

Register:TB_TASK (0x7e20b000)

field_name	start_bit	end_bit	set	clear	reset
TB_TASK_NUM	0	15	0x0000ffff	0xffff0000
TB_TASK_TEXT_FLAG	16	16	0x00010000	0xfffeffff

Register:TB_PRINTER_CTRL (0x7e20b400)

field_name	start_bit	end_bit	set	clear	reset
TB_PRINTER_CTRL_OFFSET	0	1	0x00000003	0xfffffffc
missing definiton	2	3	NA	NA	NA
TB_PRINTER_CTRL_TASKNO	4	15	0x0000fff0	0xffff000f

Register:TB_BOOT_OPT (0x7e20b504)

field_name	start_bit	end_bit	set	clear	reset
TB_BOOT_OPT_FAST_OPT	0	0	0x00000001	0xfffffffe
TB_BOOT_OPT_EIGHT_BANK	1	1	0x00000002	0xfffffffd
TB_BOOT_OPT_FPGA	2	2	0x00000004	0xfffffffb
TB_BOOT_OPT_TCL_SIM	3	3	0x00000008	0xfffffff7
TB_BOOT_OPT_ELPIDA	4	4	0x00000010	0xffffffef
TB_BOOT_OPT_SDC_BEHAV_PHY	5	5	0x00000020	0xffffffdf
TB_BOOT_OPT_NO_PRINT	6	6	0x00000040	0xffffffbf
TB_BOOT_OPT_BOOT_HALT	7	7	0x00000080	0xffffff7f
TB_BOOT_OPT_BANK_MODE	8	9	0x00000300	0xfffffcff
TB_BOOT_OPT_DONT_SET_VPU_CLK	10	10	0x00000400	0xfffffbff
missing definiton	11	30	NA	NA	NA
TB_BOOT_OPT_TB_PRESENT	31	31	0x80000000	0x7fffffff

Register:TB_BOOT_SECURE_MODE (0x7e20b508)

field_name	start_bit	end_bit	set	clear	reset
TB_BOOT_SECURE_MODE_JTAG_SECURE	0	1	0x00000003	0xfffffffc

Register:TB_BOOT_STATUS (0x7e20b50c)

field_name	start_bit	end_bit	set	clear	reset
TB_BOOT_STATUS_CPRMAN_PROGRAMMED	0	0	0x00000001	0xfffffffe

Register:TB_JTB_CONFIG (0x7e20b800)

field_name	start_bit	end_bit	set	clear	reset
TB_JTB_CONFIG_SBITS	0	4	0x0000001f	0xffffffe0
missing definiton	5	5	NA	NA	NA
TB_JTB_CONFIG_OUT_MS	6	6	0x00000040	0xffffffbf
TB_JTB_CONFIG_INV_CLK	7	7	0x00000080	0xffffff7f
TB_JTB_CONFIG_TMS_RISE	8	8	0x00000100	0xfffffeff
TB_JTB_CONFIG_TDI_RISE	9	9	0x00000200	0xfffffdff
TB_JTB_CONFIG_TDO_RISE	10	10	0x00000400	0xfffffbff
TB_JTB_CONFIG_ENABLE	11	11	0x00000800	0xfffff7ff
TB_JTB_CONFIG_D_HOLD	12	13	0x00003000	0xffffcfff
TB_JTB_CONFIG_TRSTN	14	14	0x00004000	0xffffbfff
missing definiton	15	15	NA	NA	NA
TB_JTB_CONFIG_SPEED	16	23	0x00ff0000	0xff00ffff
TB_JTB_CONFIG_BITCNT	23	29	0x3f800000	0xc07fffff
missing definiton	24	22	NA	NA	NA
missing definiton	30	30	NA	NA	NA
TB_JTB_CONFIG_BUSY	31	31	0x80000000	0x7fffffff

TE

Info

base	0x7e20e000
id	0x00746563

Registers

register name	address	type	width	mask
TE_0C	0x7e20e000	RW	32	0xffffffff
TE_0VSWIDTH	0x7e20e004	RW	32	0xffffffff
TE_0TIMER	0x7e20e008	RW	32	0xffffffff
TE_1C	0x7e20e00c	RW	32	0xffffffff
TE_1VSWIDTH	0x7e20e010	RW	32	0xffffffff
TE_1TIMER	0x7e20e014	RW	32	0xffffffff
TE_2C	0x7e20e018	RW	32	0xffffffff
TE_2VSWIDTH	0x7e20e01c	RW	32	0xffffffff
TE_2TIMER	0x7e20e020	RW	32	0xffffffff

TS

Info

base	0x7e212000
id	0x7473656e

Registers

register name	address	type	width	mask	reset
TS_TSENSCTL	0x7e212000	RW	27	0x07ffffff	0000000000
TS_TSENSSTAT	0x7e212004	RW	12	0x00000fff	0000000000

Register:TS_TSENSCTL (0x7e212000)

field_name	start_bit	end_bit	set	clear	reset
TS_TSENSCTL_PRWDW	0	0	0x00000001	0xfffffffe	0x0
TS_TSENSCTL_RSTB	1	1	0x00000002	0xfffffffd	0x0
TS_TSENSCTL_CTRL	2	4	0x0000001c	0xffffffe3	0x0
TS_TSENSCTL_EN_INT	5	5	0x00000020	0xffffffdf	0x0
TS_TSENSCTL_DIRECT	6	6	0x00000040	0xffffffbf	0x0
TS_TSENSCTL_CLR_INT	7	7	0x00000080	0xffffff7f	0x0
TS_TSENSCTL_THOLD	8	17	0x0003ff00	0xfffc00ff	0x0
TS_TSENSCTL_RSTDELAY	18	25	0x03fc0000	0xfc03ffff	0x0
TS_TSENSCTL_REGULEN	26	26	0x04000000	0xfbffffff	0x0

Register:TS_TSENSSTAT (0x7e212004)

field_name	start_bit	end_bit	set	clear	reset
TS_TSENSSTAT_DATA	0	9	0x000003ff	0xfffffc00	0x0
TS_TSENSSTAT_VALID	10	10	0x00000400	0xfffffbff	0x0
TS_TSENSSTAT_INTERUPT	11	11	0x00000800	0xfffff7ff	0x0

TXP

Info

base	0x7e004000
id	0x20763374

Registers

register name	address	type	width	mask
TXP_DST_PTR	0x7e004000	RW	32	0xfffffffe
TXP_DST_PITCH	0x7e004004	RW	32	0xfffffff0
TXP_DIM	0x7e004008	RW	28	0x0fff0fff
TXP_CTRL	0x7e00400c	RW	32	0xffffffff
TXP_PROGRESS	0x7e004010	RO	12	0x00000fff
TXP_XTRA	0x7e004018	RW	1	0x00000001

Register:TXP_DIM (0x7e004008)

field_name	start_bit	end_bit	set	clear	reset
TXP_DIM_WIDTH	0	11	0x00000fff	0xfffff000	0x0
missing definiton	12	15	NA	NA	NA
TXP_DIM_HEIGHT	16	27	0x0fff0000	0xf000ffff	0x0

Register:TXP_CTRL (0x7e00400c)

field_name	start_bit	end_bit	set	clear	reset
TXP_CTRL_GO	0	0	0x00000001	0xfffffffe
TXP_CTRL_BUSY	1	1	0x00000002	0xfffffffd
TXP_CTRL_EI	2	2	0x00000004	0xfffffffb
TXP_CTRL_FIELD	3	3	0x00000008	0xfffffff7
TXP_CTRL_TEST_MODE	4	4	0x00000010	0xffffffef
TXP_CTRL_TFORMAT	5	5	0x00000020	0xffffffdf
TXP_CTRL_TRANSPOSE	6	6	0x00000040	0xffffffbf
TXP_CTRL_LINEAR_UTILE	7	7	0x00000080	0xffffff7f
TXP_CTRL_FORMAT	8	11	0x00000f00	0xfffff0ff
TXP_CTRL_ALPHA_INVERT	12	12	0x00001000	0xffffefff
TXP_CTRL_DITHER	13	13	0x00002000	0xffffdfff
TXP_CTRL_ABORT	14	14	0x00004000	0xffffbfff
TXP_CTRL_VSTART_AT_EOF	15	15	0x00008000	0xffff7fff
TXP_CTRL_BWE	16	19	0x000f0000	0xfff0ffff	0xf
TXP_CTRL_ALPHA_ENABLE	20	20	0x00100000	0xffefffff
TXP_CTRL_POWERDOWN	21	21	0x00200000	0xffdfffff	0x0
TXP_CTRL_VERSION	22	23	0x00c00000	0xff3fffff	0x1
TXP_CTRL_PILOT	24	31	0xff000000	0x00ffffff	0x54

Register:TXP_PROGRESS (0x7e004010)

field_name	start_bit	end_bit	set	clear	reset
TXP_PROGRESS_LINES	0	11	0x00000fff	0xfffff000

Register:TXP_XTRA (0x7e004018)

field_name	start_bit	end_bit	set	clear	reset
TXP_XTRA_NOSTBY	0	0	0x00000001	0xfffffffe

UART

Info

base	0x7e201000

Registers

register name	address	type	width	mask	reset
UART_RBRTHRDLL	0x7e201000	RW
UART_IERDLM	0x7e201004	RW
UART_IIR_FCR	0x7e201008	RW
UART_LCR	0x7e20100c	RW	8	0x000000ff	0000000000
UART_MCR	0x7e201010	RW	5	0x0000001f	0000000000
UART_LSR	0x7e201014	RW	8	0x000000ff	0000000000
UART_MSR	0x7e201018	RW	8	0x000000ff	0000000000
UART_SCR	0x7e20101c	RW	8	0x000000ff	0000000000
UART_EN	0x7e201020	RW	2	0x00000002	0000000000

Unsupported defines

define	value
UART_BASE_ADDRESS	0x7e201000

Register:UART_LCR (0x7e20100c)

field_name	start_bit	end_bit	set	clear	reset
UART_LCR_DTR	0	0	0x00000001	0xfffffffe	0x0
UART_LCR_WLS	0	1	0x00000003	0xfffffffc	0x0
missing definiton	1	-1	NA	NA	NA
UART_LCR_RTS	1	1	0x00000002	0xfffffffd	0x0
UART_LCR_STB	2	2	0x00000004	0xfffffffb	0x0
UART_LCR_OUT1	2	2	0x00000004	0xfffffffb	0x0
missing definiton	2	0	NA	NA	NA
UART_LCR_OUT2	3	3	0x00000008	0xfffffff7	0x0
missing definiton	3	1	NA	NA	NA
UART_LCR_PEN	3	3	0x00000008	0xfffffff7	0x0
UART_LCR_LOOP	4	4	0x00000010	0xffffffef	0x0
UART_LCR_EPS	4	4	0x00000010	0xffffffef	0x0
missing definiton	4	2	NA	NA	NA
UART_LCR_SP	5	5	0x00000020	0xffffffdf	0x0
missing definiton	5	3	NA	NA	NA
UART_LCR_SBC	6	6	0x00000040	0xffffffbf	0x0
UART_LCR_DLAB	7	7	0x00000080	0xffffff7f	0x0

Register:UART_LSR (0x7e201014)

field_name	start_bit	end_bit	set	clear	reset
UART_LSR_DR	0	0	0x00000001	0xfffffffe	0x0
UART_LSR_OE	1	1	0x00000002	0xfffffffd	0x0
UART_LSR_PE	2	2	0x00000004	0xfffffffb	0x0
UART_LSR_FE	3	3	0x00000008	0xfffffff7	0x0
UART_LSR_BI	4	4	0x00000010	0xffffffef	0x0
UART_LSR_THRE	5	5	0x00000020	0xffffffdf	0x0
UART_LSR_TEMT	6	6	0x00000040	0xffffffbf	0x0
UART_LSR_RFE	7	7	0x00000080	0xffffff7f	0x0

Register:UART_MSR (0x7e201018)

field_name	start_bit	end_bit	set	clear	reset
UART_MSR_DCTS	0	0	0x00000001	0xfffffffe	0x0
UART_MSR_DDSR	1	1	0x00000002	0xfffffffd	0x0
UART_MSR_TERI	2	2	0x00000004	0xfffffffb	0x0
UART_MSR_DDCD	3	3	0x00000008	0xfffffff7	0x0
UART_MSR_CTS	4	4	0x00000010	0xffffffef	0x0
UART_MSR_DSR	5	5	0x00000020	0xffffffdf	0x0
UART_MSR_RI	6	6	0x00000040	0xffffffbf	0x0
UART_MSR_DCD	7	7	0x00000080	0xffffff7f	0x0

USB

Info

base	0x7e980000
id	0x75736230

Registers

register name	address	type	width	mask
USB_GOTGCTL	0x7e980000	RW	20	0x000f0f03
USB_GOTGINT	0x7e980004	RW	20	0x000e0304
USB_GAHBCFG	0x7e980008	RW	9	0x000001bf
USB_GUSBCFG	0x7e98000c	RW	32	0xe3ffbfff
USB_GRSTCTL	0x7e980010	RW	32	0xc00007ff
USB_GINTSTS	0x7e980014	RW	32	0xffffffff
USB_GINTMSK	0x7e980018	RW	32	0xf77effff
USB_GRXSTSR	0x7e98001c	RW	32	0xffffffff
USB_GRXSTSP	0x7e980020	RW	25	0x01ffffff
USB_GRXFSIZ	0x7e980024	RW	16	0x0000ffff
USB_GNPTXFSIZ	0x7e980028	RW	32	0xffffffff
USB_GNPTXSTS	0x7e98002c	RW	31	0x7fffffff
USB_GI2CCTL	0x7e980030	RW	32	0xdfffffff
USB_GPVNDCTL	0x7e980034	RW	32	0x8e7f3fff
USB_GGPIO	0x7e980038	RW	32	0xffffffff
USB_GUID	0x7e98003c	RW	32	0xffffffff
USB_GSNPSID	0x7e980040	RW	32	0xffffffff
USB_GHWCFG1	0x7e980044	RW	32	0xffffffff
USB_GHWCFG2	0x7e980048	RW	31	0x7fcfffff
USB_GHWCFG3	0x7e98004c	RW	32	0xffff0fff
USB_GHWCFG4	0x7e980050	RW	32	0xffffc03f
USB_GAXIDEV	0x7e980054	RW	32	0xffffffff
USB_GLPMCFG	0x7e980054	RW	32	0xffffffff
USB_MDIO_CSR	0x7e980080	RW
USB_GMDIOCSR	0x7e980080	RW	16	0x0000ffff
USB_MDIO_GEN	0x7e980084	RW
USB_GMDIOGEN	0x7e980084	RW	32	0xffffffff
USB_GVBUSDRV	0x7e980088	RW	16	0x0000ffff
USB_VBUS_DRV	0x7e980088	RW
USB_HPTXFSIZ	0x7e980100	RW	32	0xffffffff
USB_DPTXFSIZ1	0x7e980104	RW	32	0xffffffff
USB_DIEPTXF1	0x7e980104	RW	32	0xffffffff
USB_DPTXFSIZ2	0x7e980108	RW	32	0xffffffff
USB_DIEPTXF2	0x7e980108	RW	32	0xffffffff
USB_DPTXFSIZ3	0x7e98010c	RW	32	0xffffffff
USB_DIEPTXF3	0x7e98010c	RW	32	0xffffffff
USB_DIEPTXF4	0x7e980110	RW	32	0xffffffff
USB_DPTXFSIZ4	0x7e980110	RW	32	0xffffffff
USB_DIEPTXF5	0x7e980114	RW	32	0xffffffff
USB_DPTXFSIZ5	0x7e980114	RW	32	0xffffffff
USB_DPTXFSIZ6	0x7e980118	RW	32	0xffffffff
USB_DIEPTXF6	0x7e980118	RW	32	0xffffffff
USB_DIEPTXF7	0x7e98011c	RW	32	0xffffffff
USB_DPTXFSIZ7	0x7e98011c	RW	32	0xffffffff
USB_DPTXFSIZ8	0x7e980120	RW	32	0xffffffff
USB_DIEPTXF8	0x7e980120	RW	32	0xffffffff
USB_DIEPTXF9	0x7e980124	RW	32	0xffffffff
USB_DPTXFSIZ9	0x7e980124	RW	32	0xffffffff
USB_DIEPTXF10	0x7e980128	RW	32	0xffffffff
USB_DPTXFSIZ10	0x7e980128	RW	32	0xffffffff
USB_DIEPTXF11	0x7e98012c	RW	32	0xffffffff
USB_DPTXFSIZ11	0x7e98012c	RW	32	0xffffffff
USB_DIEPTXF12	0x7e980130	RW	32	0xffffffff
USB_DPTXFSIZ12	0x7e980130	RW	32	0xffffffff
USB_DPTXFSIZ13	0x7e980134	RW	32	0xffffffff
USB_DIEPTXF13	0x7e980134	RW	32	0xffffffff
USB_DIEPTXF14	0x7e980138	RW	32	0xffffffff
USB_DPTXFSIZ14	0x7e980138	RW	32	0xffffffff
USB_DPTXFSIZ15	0x7e98013c	RW	32	0xffffffff
USB_DIEPTXF15	0x7e98013c	RW	32	0xffffffff
USB_HCFG	0x7e980400	RW	3	0x00000007
USB_HFIR	0x7e980404	RW	16	0x0000ffff
USB_HFNUM	0x7e980408	RW	32	0xffffffff
USB_HPTXSTS	0x7e980410	RW	32	0xffffffff
USB_HAINT	0x7e980414	RW	32	0xffffffff
USB_HAINTMSK	0x7e980418	RW	32	0xffffffff
USB_HPRT	0x7e980440	RW	19	0x0007fdff
USB_HCCHAR0	0x7e980500	RW	32	0xffffffff
USB_HCSPLT0	0x7e980504	RW	32	0xffffffff
USB_HCINT0	0x7e980508	RW	32	0xffffffff
USB_HCINTMSK0	0x7e98050c	RW	32	0xffffffff
USB_HCTSIZ0	0x7e980510	RW	32	0xffffffff
USB_HCDMA0	0x7e980514	RW	32	0xffffffff
USB_HCCHAR1	0x7e980520	RW	32	0xffffffff
USB_HCSPLT1	0x7e980524	RW	32	0xffffffff
USB_HCINT1	0x7e980528	RW	32	0xffffffff
USB_HCINTMSK1	0x7e98052c	RW	32	0xffffffff
USB_HCTSIZ1	0x7e980530	RW	32	0xffffffff
USB_HCDMA1	0x7e980534	RW	32	0xffffffff
USB_HCCHAR2	0x7e980540	RW	32	0xffffffff
USB_HCSPLT2	0x7e980544	RW	32	0xffffffff
USB_HCINT2	0x7e980548	RW	32	0xffffffff
USB_HCINTMSK2	0x7e98054c	RW	32	0xffffffff
USB_HCTSIZ2	0x7e980550	RW	32	0xffffffff
USB_HCDMA2	0x7e980554	RW	32	0xffffffff
USB_HCCHAR3	0x7e980560	RW	32	0xffffffff
USB_HCSPLT3	0x7e980564	RW	32	0xffffffff
USB_HCINT3	0x7e980568	RW	32	0xffffffff
USB_HCINTMSK3	0x7e98056c	RW	32	0xffffffff
USB_HCTSIZ3	0x7e980570	RW	32	0xffffffff
USB_HCDMA3	0x7e980574	RW	32	0xffffffff
USB_HCCHAR4	0x7e980580	RW	32	0xffffffff
USB_HCSPLT4	0x7e980584	RW	32	0xffffffff
USB_HCINT4	0x7e980588	RW	32	0xffffffff
USB_HCINTMSK4	0x7e98058c	RW	32	0xffffffff
USB_HCTSIZ4	0x7e980590	RW	32	0xffffffff
USB_HCDMA4	0x7e980594	RW	32	0xffffffff
USB_HCCHAR5	0x7e9805a0	RW	32	0xffffffff
USB_HCSPLT5	0x7e9805a4	RW	32	0xffffffff
USB_HCINT5	0x7e9805a8	RW	32	0xffffffff
USB_HCINTMSK5	0x7e9805ac	RW	32	0xffffffff
USB_HCTSIZ5	0x7e9805b0	RW	32	0xffffffff
USB_HCDMA5	0x7e9805b4	RW	32	0xffffffff
USB_HCCHAR6	0x7e9805c0	RW	32	0xffffffff
USB_HCSPLT6	0x7e9805c4	RW	32	0xffffffff
USB_HCINT6	0x7e9805c8	RW	32	0xffffffff
USB_HCINTMSK6	0x7e9805cc	RW	32	0xffffffff
USB_HCTSIZ6	0x7e9805d0	RW	32	0xffffffff
USB_HCDMA6	0x7e9805d4	RW	32	0xffffffff
USB_HCCHAR7	0x7e9805e0	RW	32	0xffffffff
USB_HCSPLT7	0x7e9805e4	RW	32	0xffffffff
USB_HCINT7	0x7e9805e8	RW	32	0xffffffff
USB_HCINTMSK7	0x7e9805ec	RW	32	0xffffffff
USB_HCTSIZ7	0x7e9805f0	RW	32	0xffffffff
USB_HCDMA7	0x7e9805f4	RW	32	0xffffffff
USB_DCFG	0x7e980800	RW	26	0x03fc1ff7
USB_DCTL	0x7e980804	RW	16	0x0000efff
USB_DSTS	0x7e980808	RW	22	0x003fff0f
USB_DIEPMSK	0x7e980810	RW	32	0xffffffff
USB_DOEPMSK	0x7e980814	RW	32	0xffffffff
USB_DAINT	0x7e980818	RW	32	0xffffffff
USB_DAINTMSK	0x7e98081c	RW	32	0xffffffff
USB_DTKNQR1	0x7e980820	RW	32	0xffffffff
USB_DTKNQR2	0x7e980824	RW	32	0xffffffff
USB_DVBUSDIS	0x7e980828	RW	16	0x0000ffff
USB_DVBUSPULSE	0x7e98082c	RW	12	0x00000fff
USB_DTKNQR3	0x7e980830	RW	32	0xffffffff
USB_DTHRCTL	0x7e980830	RW	28	0x0fff0fff
USB_DIEPEMPMSK	0x7e980834	RW	16	0x0000ffff
USB_DTKNQR4	0x7e980834	RW	32	0xffffffff
USB_DIEPCTL0	0x7e980900	RW	32	0xffffffff
USB_DIEPINT0	0x7e980908	RW	32	0xffffffff
USB_DIEPTSIZ0	0x7e980910	RW	32	0xffffffff
USB_DIEPDMA0	0x7e980914	RW	32	0xffffffff
USB_DTXFSTS0	0x7e980918	RW	32	0xffffffff
USB_DIEPDMAB0	0x7e980918	RW	32	0xffffffff
USB_DIEPCTL1	0x7e980920	RW	32	0xffffffff
USB_DIEPINT1	0x7e980928	RW	32	0xffffffff
USB_DIEPTSIZ1	0x7e980930	RW	32	0xffffffff
USB_DIEPDMA1	0x7e980934	RW	32	0xffffffff
USB_DTXFSTS1	0x7e980938	RW	32	0xffffffff
USB_DIEPDMAB1	0x7e980938	RW	32	0xffffffff
USB_DIEPCTL2	0x7e980940	RW	32	0xffffffff
USB_DIEPINT2	0x7e980948	RW	32	0xffffffff
USB_DIEPTSIZ2	0x7e980950	RW	32	0xffffffff
USB_DIEPDMA2	0x7e980954	RW	32	0xffffffff
USB_DTXFSTS2	0x7e980958	RW	32	0xffffffff
USB_DIEPDMAB2	0x7e980958	RW	32	0xffffffff
USB_DIEPCTL3	0x7e980960	RW	32	0xffffffff
USB_DIEPINT3	0x7e980968	RW	32	0xffffffff
USB_DIEPTSIZ3	0x7e980970	RW	32	0xffffffff
USB_DIEPDMA3	0x7e980974	RW	32	0xffffffff
USB_DTXFSTS3	0x7e980978	RW	32	0xffffffff
USB_DIEPDMAB3	0x7e980978	RW	32	0xffffffff
USB_DIEPCTL4	0x7e980980	RW	32	0xffffffff
USB_DIEPINT4	0x7e980988	RW	32	0xffffffff
USB_DIEPTSIZ4	0x7e980990	RW	32	0xffffffff
USB_DIEPDMA4	0x7e980994	RW	32	0xffffffff
USB_DTXFSTS4	0x7e980998	RW	32	0xffffffff
USB_DIEPDMAB4	0x7e980998	RW	32	0xffffffff
USB_DIEPCTL5	0x7e9809a0	RW	32	0xffffffff
USB_DIEPINT5	0x7e9809a8	RW	32	0xffffffff
USB_DIEPTSIZ5	0x7e9809b0	RW	32	0xffffffff
USB_DIEPDMA5	0x7e9809b4	RW	32	0xffffffff
USB_DTXFSTS5	0x7e9809b8	RW	32	0xffffffff
USB_DIEPDMAB5	0x7e9809b8	RW	32	0xffffffff
USB_DIEPCTL6	0x7e9809c0	RW	32	0xffffffff
USB_DIEPINT6	0x7e9809c8	RW	32	0xffffffff
USB_DIEPTSIZ6	0x7e9809d0	RW	32	0xffffffff
USB_DIEPDMA6	0x7e9809d4	RW	32	0xffffffff
USB_DIEPDMAB6	0x7e9809d8	RW	32	0xffffffff
USB_DTXFSTS6	0x7e9809d8	RW	32	0xffffffff
USB_DIEPCTL7	0x7e9809e0	RW	32	0xffffffff
USB_DIEPINT7	0x7e9809e8	RW	32	0xffffffff
USB_DIEPTSIZ7	0x7e9809f0	RW	32	0xffffffff
USB_DIEPDMA7	0x7e9809f4	RW	32	0xffffffff
USB_DTXFSTS7	0x7e9809f8	RW	32	0xffffffff
USB_DIEPDMAB7	0x7e9809f8	RW	32	0xffffffff
USB_DIEPCTL8	0x7e980a00	RW	32	0xffffffff
USB_DIEPINT8	0x7e980a08	RW	32	0xffffffff
USB_DIEPTSIZ8	0x7e980a10	RW	32	0xffffffff
USB_DIEPDMA8	0x7e980a14	RW	32	0xffffffff
USB_DTXFSTS8	0x7e980a18	RW	32	0xffffffff
USB_DIEPDMAB8	0x7e980a18	RW	32	0xffffffff
USB_DIEPCTL9	0x7e980a20	RW	32	0xffffffff
USB_DIEPINT9	0x7e980a28	RW	32	0xffffffff
USB_DIEPTSIZ9	0x7e980a30	RW	32	0xffffffff
USB_DIEPDMA9	0x7e980a34	RW	32	0xffffffff
USB_DIEPDMAB9	0x7e980a38	RW	32	0xffffffff
USB_DTXFSTS9	0x7e980a38	RW	32	0xffffffff
USB_DIEPCTL10	0x7e980a40	RW	32	0xffffffff
USB_DIEPINT10	0x7e980a48	RW	32	0xffffffff
USB_DIEPTSIZ10	0x7e980a50	RW	32	0xffffffff
USB_DIEPDMA10	0x7e980a54	RW	32	0xffffffff
USB_DIEPDMAB10	0x7e980a58	RW	32	0xffffffff
USB_DTXFSTS10	0x7e980a58	RW	32	0xffffffff
USB_DIEPCTL11	0x7e980a60	RW	32	0xffffffff
USB_DIEPINT11	0x7e980a68	RW	32	0xffffffff
USB_DIEPTSIZ11	0x7e980a70	RW	32	0xffffffff
USB_DIEPDMA11	0x7e980a74	RW	32	0xffffffff
USB_DIEPDMAB11	0x7e980a78	RW	32	0xffffffff
USB_DTXFSTS11	0x7e980a78	RW	32	0xffffffff
USB_DIEPCTL12	0x7e980a80	RW	32	0xffffffff
USB_DIEPINT12	0x7e980a88	RW	32	0xffffffff
USB_DIEPTSIZ12	0x7e980a90	RW	32	0xffffffff
USB_DIEPDMA12	0x7e980a94	RW	32	0xffffffff
USB_DIEPDMAB12	0x7e980a98	RW	32	0xffffffff
USB_DTXFSTS12	0x7e980a98	RW	32	0xffffffff
USB_DIEPCTL13	0x7e980aa0	RW	32	0xffffffff
USB_DIEPINT13	0x7e980aa8	RW	32	0xffffffff
USB_DIEPTSIZ13	0x7e980ab0	RW	32	0xffffffff
USB_DIEPDMA13	0x7e980ab4	RW	32	0xffffffff
USB_DTXFSTS13	0x7e980ab8	RW	32	0xffffffff
USB_DIEPDMAB13	0x7e980ab8	RW	32	0xffffffff
USB_DIEPCTL14	0x7e980ac0	RW	32	0xffffffff
USB_DIEPINT14	0x7e980ac8	RW	32	0xffffffff
USB_DIEPTSIZ14	0x7e980ad0	RW	32	0xffffffff
USB_DIEPDMA14	0x7e980ad4	RW	32	0xffffffff
USB_DTXFSTS14	0x7e980ad8	RW	32	0xffffffff
USB_DIEPDMAB14	0x7e980ad8	RW	32	0xffffffff
USB_DIEPCTL15	0x7e980ae0	RW	32	0xffffffff
USB_DIEPINT15	0x7e980ae8	RW	32	0xffffffff
USB_DIEPTSIZ15	0x7e980af0	RW	32	0xffffffff
USB_DIEPDMA15	0x7e980af4	RW	32	0xffffffff
USB_DTXFSTS15	0x7e980af8	RW	32	0xffffffff
USB_DIEPDMAB15	0x7e980af8	RW	32	0xffffffff
USB_DOEPCTL0	0x7e980b00	RW	32	0xffffffff
USB_DOEPINT0	0x7e980b08	RW	32	0xffffffff
USB_DOEPTSIZ0	0x7e980b10	RW	32	0xffffffff
USB_DOEPDMA0	0x7e980b14	RW	32	0xffffffff
USB_DOEPDMAB5	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB12	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB6	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB13	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB2	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB3	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB4	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB8	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB11	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB10	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB1	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB7	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB9	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB15	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB14	0x7e980b1c	RW	32	0xffffffff
USB_DOEPDMAB0	0x7e980b1c	RW	32	0xffffffff
USB_DOEPCTL1	0x7e980b20	RW	32	0xffffffff
USB_DOEPINT1	0x7e980b28	RW	32	0xffffffff
USB_DOEPTSIZ1	0x7e980b30	RW	32	0xffffffff
USB_DOEPDMA1	0x7e980b34	RW	32	0xffffffff
USB_DOEPCTL2	0x7e980b40	RW	32	0xffffffff
USB_DOEPINT2	0x7e980b48	RW	32	0xffffffff
USB_DOEPTSIZ2	0x7e980b50	RW	32	0xffffffff
USB_DOEPDMA2	0x7e980b54	RW	32	0xffffffff
USB_DOEPCTL3	0x7e980b60	RW	32	0xffffffff
USB_DOEPINT3	0x7e980b68	RW	32	0xffffffff
USB_DOEPTSIZ3	0x7e980b70	RW	32	0xffffffff
USB_DOEPDMA3	0x7e980b74	RW	32	0xffffffff
USB_DOEPCTL4	0x7e980b80	RW	32	0xffffffff
USB_DOEPINT4	0x7e980b88	RW	32	0xffffffff
USB_DOEPTSIZ4	0x7e980b90	RW	32	0xffffffff
USB_DOEPDMA4	0x7e980b94	RW	32	0xffffffff
USB_DOEPCTL5	0x7e980ba0	RW	32	0xffffffff
USB_DOEPINT5	0x7e980ba8	RW	32	0xffffffff
USB_DOEPTSIZ5	0x7e980bb0	RW	32	0xffffffff
USB_DOEPDMA5	0x7e980bb4	RW	32	0xffffffff
USB_DOEPCTL6	0x7e980bc0	RW	32	0xffffffff
USB_DOEPINT6	0x7e980bc8	RW	32	0xffffffff
USB_DOEPTSIZ6	0x7e980bd0	RW	32	0xffffffff
USB_DOEPDMA6	0x7e980bd4	RW	32	0xffffffff
USB_DOEPCTL7	0x7e980be0	RW	32	0xffffffff
USB_DOEPINT7	0x7e980be8	RW	32	0xffffffff
USB_DOEPTSIZ7	0x7e980bf0	RW	32	0xffffffff
USB_DOEPDMA7	0x7e980bf4	RW	32	0xffffffff
USB_DOEPCTL8	0x7e980c00	RW	32	0xffffffff
USB_DOEPINT8	0x7e980c08	RW	32	0xffffffff
USB_DOEPTSIZ8	0x7e980c10	RW	32	0xffffffff
USB_DOEPDMA8	0x7e980c14	RW	32	0xffffffff
USB_DOEPCTL9	0x7e980c20	RW	32	0xffffffff
USB_DOEPINT9	0x7e980c28	RW	32	0xffffffff
USB_DOEPTSIZ9	0x7e980c30	RW	32	0xffffffff
USB_DOEPDMA9	0x7e980c34	RW	32	0xffffffff
USB_DOEPCTL10	0x7e980c40	RW	32	0xffffffff
USB_DOEPINT10	0x7e980c48	RW	32	0xffffffff
USB_DOEPTSIZ10	0x7e980c50	RW	32	0xffffffff
USB_DOEPDMA10	0x7e980c54	RW	32	0xffffffff
USB_DOEPCTL11	0x7e980c60	RW	32	0xffffffff
USB_DOEPINT11	0x7e980c68	RW	32	0xffffffff
USB_DOEPTSIZ11	0x7e980c70	RW	32	0xffffffff
USB_DOEPDMA11	0x7e980c74	RW	32	0xffffffff
USB_DOEPCTL12	0x7e980c80	RW	32	0xffffffff
USB_DOEPINT12	0x7e980c88	RW	32	0xffffffff
USB_DOEPTSIZ12	0x7e980c90	RW	32	0xffffffff
USB_DOEPDMA12	0x7e980c94	RW	32	0xffffffff
USB_DOEPCTL13	0x7e980ca0	RW	32	0xffffffff
USB_DOEPINT13	0x7e980ca8	RW	32	0xffffffff
USB_DOEPTSIZ13	0x7e980cb0	RW	32	0xffffffff
USB_DOEPDMA13	0x7e980cb4	RW	32	0xffffffff
USB_DOEPCTL14	0x7e980cc0	RW	32	0xffffffff
USB_DOEPINT14	0x7e980cc8	RW	32	0xffffffff
USB_DOEPTSIZ14	0x7e980cd0	RW	32	0xffffffff
USB_DOEPDMA14	0x7e980cd4	RW	32	0xffffffff
USB_DOEPCTL15	0x7e980ce0	RW	32	0xffffffff
USB_DOEPINT15	0x7e980ce8	RW	32	0xffffffff
USB_DOEPTSIZ15	0x7e980cf0	RW	32	0xffffffff
USB_DOEPDMA15	0x7e980cf4	RW	32	0xffffffff
USB_PCGCR	0x7e980e00	RW	4	0x0000000f
USB_DFIFO0	0x7e981000	RW	32	0xffffffff
USB_DFIFO1	0x7e982000	RW	32	0xffffffff
USB_DFIFO2	0x7e983000	RW	32	0xffffffff
USB_DFIFO3	0x7e984000	RW	32	0xffffffff
USB_DFIFO4	0x7e985000	RW	32	0xffffffff
USB_DFIFO5	0x7e986000	RW	32	0xffffffff
USB_DFIFO6	0x7e987000	RW	32	0xffffffff
USB_DFIFO7	0x7e988000	RW	32	0xffffffff
USB_DFIFO8	0x7e989000	RW	32	0xffffffff
USB_DFIFO9	0x7e98a000	RW	32	0xffffffff
USB_DFIFO10	0x7e98b000	RW	32	0xffffffff
USB_DFIFO11	0x7e98c000	RW	32	0xffffffff
USB_DFIFO12	0x7e98d000	RW	32	0xffffffff
USB_DFIFO13	0x7e98e000	RW	32	0xffffffff
USB_DFIFO14	0x7e98f000	RW	32	0xffffffff
USB_DFIFO15	0x7e990000	RW	32	0xffffffff

Unsupported defines

define	value
USB_DFIFOn(n)	MACRO
USB_DIEPCTLn(n)	MACRO
USB_DIEPDMAn(n)	MACRO
USB_DIEPINT_off(n)	MACRO
USB_DIEPTSIZn(n)	MACRO
USB_DTXFSTSn(n)	MACRO
USB_HCINT_off(n)	MACRO
USB_VBUS_DRV_AVALID	8
USB_VBUS_DRV_BVALID	4
USB_VBUS_DRV_CHRGVBUS	32
USB_VBUS_DRV_DISCHRGVBUS	64
USB_VBUS_DRV_DRVVBUS	16
USB_VBUS_DRV_SESSEND	1
USB_VBUS_DRV_VBUSVALID	2

Register:USB_GOTGCTL (0x7e980000)

field_name	start_bit	end_bit	set	clear	reset
USB_GOTGCTL_SES_REQ_SCS	0	0	0x00000001	0xfffffffe	0x0
USB_GOTGCTL_SES_REQ	1	1	0x00000002	0xfffffffd	0x0
missing definiton	2	7	NA	NA	NA
USB_GOTGCTL_HST_NEG_SCS	8	8	0x00000100	0xfffffeff	0x0
USB_GOTGCTL_HNP_REQ	9	9	0x00000200	0xfffffdff	0x0
USB_GOTGCTL_HST_SET_HNP_EN	10	10	0x00000400	0xfffffbff	0x0
USB_GOTGCTL_DEV_HNP_EN	11	11	0x00000800	0xfffff7ff	0x0
missing definiton	12	15	NA	NA	NA
USB_GOTGCTL_CON_ID_STS	16	16	0x00010000	0xfffeffff	0x0
USB_GOTGCTL_DBNC_TIME	17	17	0x00020000	0xfffdffff	0x0
USB_GOTGCTL_A_SES_VLD	18	18	0x00040000	0xfffbffff	0x0
USB_GOTGCTL_B_SES_VLD	19	19	0x00080000	0xfff7ffff	0x0

Register:USB_GOTGINT (0x7e980004)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	1	NA	NA	NA
USB_GOTGINT_SES_END_DET	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	7	NA	NA	NA
USB_GOTGINT_SES_REQ_SUC_STS_CHG	8	8	0x00000100	0xfffffeff	0x0
USB_GOTGINT_HST_NEG_SUC_STS_CHG	9	9	0x00000200	0xfffffdff	0x0
missing definiton	10	16	NA	NA	NA
USB_GOTGINT_HST_NEG_DET	17	17	0x00020000	0xfffdffff	0x0
USB_GOTGINT_A_DEV_TOUT_CHG	18	18	0x00040000	0xfffbffff	0x0
USB_GOTGINT_DBNCE_DONE	19	19	0x00080000	0xfff7ffff	0x0

Register:USB_GAHBCFG (0x7e980008)

field_name	start_bit	end_bit	set	clear	reset
USB_GAHBCFG_GLBL_INTR_MSK	0	0	0x00000001	0xfffffffe	0x0
USB_GAHBCFG_H_BST_LEN	1	4	0x0000001e	0xffffffe1	0x0
USB_GAHBCFG_DMA_EN	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	6	NA	NA	NA
USB_GAHBCFG_NP_TXF_EMP_LVL	7	7	0x00000080	0xffffff7f	0x0
USB_GAHBCFG_P_TXF_EMP_LVL	8	8	0x00000100	0xfffffeff	0x0

Register:USB_GUSBCFG (0x7e98000c)

field_name	start_bit	end_bit	set	clear	reset
USB_GUSBCFG_TOUT_CAL	0	2	0x00000007	0xfffffff8	0x0
USB_GUSBCFG_PHY_IF	3	3	0x00000008	0xfffffff7	0x0
USB_GUSBCFG_ULPI_UTMI_SEL	4	4	0x00000010	0xffffffef	0x0
USB_GUSBCFG_FS_INTF	5	5	0x00000020	0xffffffdf	0x0
USB_GUSBCFG_PHY_SEL	6	6	0x00000040	0xffffffbf	0x0
USB_GUSBCFG_DDR_SEL	7	7	0x00000080	0xffffff7f	0x0
USB_GUSBCFG_SRP_CAP	8	8	0x00000100	0xfffffeff	0x0
USB_GUSBCFG_HNP_CAP	9	9	0x00000200	0xfffffdff	0x0
USB_GUSBCFG_USB_TRD_TIM	10	13	0x00003c00	0xffffc3ff	0x0
missing definiton	14	14	NA	NA	NA
USB_GUSBCFG_PHY_LPWR_CLK_SEL	15	15	0x00008000	0xffff7fff	0x0
USB_GUSBCFG_OTG_I2C_SEL	16	16	0x00010000	0xfffeffff	0x0
USB_GUSBCFG_ULPI_FS_LS	17	17	0x00020000	0xfffdffff	0x0
USB_GUSBCFG_ULPI_AUTO_RES	18	18	0x00040000	0xfffbffff	0x0
USB_GUSBCFG_ULPI_CLK_SUS_M	19	19	0x00080000	0xfff7ffff	0x0
USB_GUSBCFG_ULPI_EXT_VBUS_DRV	20	20	0x00100000	0xffefffff	0x0
USB_GUSBCFG_ULPI_EXT_VBUS_IND	21	21	0x00200000	0xffdfffff	0x0
USB_GUSBCFG_TERM_SEL_DL_PULSE	22	22	0x00400000	0xffbfffff	0x0
USB_GUSBCFG_IND_COMP	23	23	0x00800000	0xff7fffff	0x0
USB_GUSBCFG_IND_PASS_THRU	24	24	0x01000000	0xfeffffff	0x0
USB_GUSBCFG_ULPI_IF_PROT_DIS	25	25	0x02000000	0xfdffffff	0x0
missing definiton	26	28	NA	NA	NA
USB_GUSBCFG_FORCE_HST_MODE	29	29	0x20000000	0xdfffffff	0x0
USB_GUSBCFG_FORCE_DEV_MODE	30	30	0x40000000	0xbfffffff	0x0
USB_GUSBCFG_CORRUPT_TX	31	31	0x80000000	0x7fffffff	0x0

Register:USB_GRSTCTL (0x7e980010)

field_name	start_bit	end_bit	set	clear	reset
USB_GRSTCTL_C_SFT_RST	0	0	0x00000001	0xfffffffe	0x0
USB_GRSTCTL_H_SFT_RST	1	1	0x00000002	0xfffffffd	0x0
USB_GRSTCTL_FRM_CNTR_RST	2	2	0x00000004	0xfffffffb	0x0
USB_GRSTCTL_INT_TKN_Q_FLSH	3	3	0x00000008	0xfffffff7	0x0
USB_GRSTCTL_RXF_FLSH	4	4	0x00000010	0xffffffef	0x0
USB_GRSTCTL_TXF_FLSH	5	5	0x00000020	0xffffffdf	0x0
USB_GRSTCTL_TXF_NUM	6	10	0x000007c0	0xfffff83f	0x0
missing definiton	11	29	NA	NA	NA
USB_GRSTCTL_DMA_REQ	30	30	0x40000000	0xbfffffff	0x0
USB_GRSTCTL_AHB_IDLE	31	31	0x80000000	0x7fffffff	0x0

Register:USB_GINTMSK (0x7e980018)

field_name	start_bit	end_bit	set	clear	reset
USB_GINTMSK_CUR_MOD	0	0	0x00000001	0xfffffffe	0x0
USB_GINTMSK_MODE_MIS	1	1	0x00000002	0xfffffffd	0x0
USB_GINTMSK_OTG_INT	2	2	0x00000004	0xfffffffb	0x0
USB_GINTMSK_SOF	3	3	0x00000008	0xfffffff7	0x0
USB_GINTMSK_RXF_LVL	4	4	0x00000010	0xffffffef	0x0
USB_GINTMSK_NP_TXF_EMP	5	5	0x00000020	0xffffffdf	0x0
USB_GINTMSK_GIN_N_NAK_EFF	6	6	0x00000040	0xffffffbf	0x0
USB_GINTMSK_GOUT_NAK_EFF	7	7	0x00000080	0xffffff7f	0x0
USB_GINTMSK_ULPI_CK_INT	8	8	0x00000100	0xfffffeff	0x0
USB_GINTMSK_I2C_INT	9	9	0x00000200	0xfffffdff	0x0
USB_GINTMSK_ERLY_SUSP	10	10	0x00000400	0xfffffbff	0x0
USB_GINTMSK_USB_SUSP	11	11	0x00000800	0xfffff7ff	0x0
USB_GINTMSK_USB_RST	12	12	0x00001000	0xffffefff	0x0
USB_GINTMSK_ENUM_DONE	13	13	0x00002000	0xffffdfff	0x0
USB_GINTMSK_ISO_OUT_DROP	14	14	0x00004000	0xffffbfff	0x0
USB_GINTMSK_EOPF	15	15	0x00008000	0xffff7fff	0x0
missing definiton	16	16	NA	NA	NA
USB_GINTMSK_EP_MIS	17	17	0x00020000	0xfffdffff	0x0
USB_GINTMSK_IEP_INT	18	18	0x00040000	0xfffbffff	0x0
USB_GINTMSK_OEP_INT	19	19	0x00080000	0xfff7ffff	0x0
USB_GINTMSK_INCOMPL_ISO_IN	20	20	0x00100000	0xffefffff	0x0
USB_GINTMSK_INCOMPL_ISO_OUT	21	21	0x00200000	0xffdfffff	0x0
USB_GINTMSK_INCOMPL_P	21	21	0x00200000	0xffdfffff	0x0
missing definiton	22	20	NA	NA	NA
USB_GINTMSK_FET_SUSP	22	22	0x00400000	0xffbfffff	0x0
missing definiton	23	23	NA	NA	NA
USB_GINTMSK_PRT_INT	24	24	0x01000000	0xfeffffff	0x0
USB_GINTMSK_HCH_INT	25	25	0x02000000	0xfdffffff	0x0
USB_GINTMSK_P_TXF_EMP	26	26	0x04000000	0xfbffffff	0x0
missing definiton	27	27	NA	NA	NA
USB_GINTMSK_CON_ID_STS_CHNG	28	28	0x10000000	0xefffffff	0x0
USB_GINTMSK_DISCONN_INT	29	29	0x20000000	0xdfffffff	0x0
USB_GINTMSK_SESS_REQ_INT	30	30	0x40000000	0xbfffffff	0x0
USB_GINTMSK_WK_UP_INT	31	31	0x80000000	0x7fffffff	0x0

Register:USB_GRXSTSP (0x7e980020)

field_name	start_bit	end_bit	set	clear	reset
USB_GRXSTSP_HST_CH_NUM	0	3	0x0000000f	0xfffffff0	0x0
USB_GRXSTSP_DEV_EP_NUM	0	3	0x0000000f	0xfffffff0	0x0
USB_GRXSTSP_DEV_BCNT	4	14	0x00007ff0	0xffff800f	0x0
missing definiton	4	-1	NA	NA	NA
USB_GRXSTSP_HST_BCNT	4	14	0x00007ff0	0xffff800f	0x0
USB_GRXSTSP_HST_DPID	15	16	0x00018000	0xfffe7fff	0x0
missing definiton	15	3	NA	NA	NA
USB_GRXSTSP_DEV_DPID	15	16	0x00018000	0xfffe7fff	0x0
USB_GRXSTSP_DEV_PKT_STS	17	20	0x001e0000	0xffe1ffff	0x0
missing definiton	17	14	NA	NA	NA
USB_GRXSTSP_HST_PKT_STS	17	20	0x001e0000	0xffe1ffff	0x0
USB_GRXSTSP_DEV_FN	21	24	0x01e00000	0xfe1fffff	0x0
missing definiton	21	16	NA	NA	NA

Register:USB_GRXFSIZ (0x7e980024)

field_name	start_bit	end_bit	set	clear	reset
USB_GRXFSIZ_GRXF_DEP	0	15	0x0000ffff	0xffff0000	0x0

Register:USB_GNPTXFSIZ (0x7e980028)

field_name	start_bit	end_bit	set	clear	reset
USB_GNPTXFSIZ_NP_TXF_ST_ADDR	0	15	0x0000ffff	0xffff0000	0x0
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR	0	15	0x0000ffff	0xffff0000	0x0
USB_GNPTXFSIZ_IN_EP_TXF0_DEP	16	31	0xffff0000	0x0000ffff	0x0
missing definiton	16	-1	NA	NA	NA
USB_GNPTXFSIZ_NP_TXF_DEP	16	31	0xffff0000	0x0000ffff	0x0
missing definiton	32	15	NA	NA	NA

Register:USB_GNPTXSTS (0x7e98002c)

field_name	start_bit	end_bit	set	clear	reset
USB_GNPTXSTS_TXF_SPC_AVAIL	0	15	0x0000ffff	0xffff0000	0x0
USB_GNPTXSTS_TX_Q_SPC_AVAIL	16	23	0x00ff0000	0xff00ffff	0x0
USB_GNPTXSTS_TX_Q_TOP	24	30	0x7f000000	0x80ffffff	0x0

Register:USB_GI2CCTL (0x7e980030)

field_name	start_bit	end_bit	set	clear	reset
USB_GI2CCTL_RW_DATA	0	7	0x000000ff	0xffffff00	0x0
USB_GI2CCTL_REG_ADDR	8	15	0x0000ff00	0xffff00ff	0x0
USB_GI2CCTL_ADDR	16	22	0x007f0000	0xff80ffff	0x0
USB_GI2CCTL_EN	23	23	0x00800000	0xff7fffff	0x0
missing definiton	24	24	NA	NA	NA
USB_GI2CCTL_SUSP_CTL	25	25	0x02000000	0xfdffffff	0x0
USB_GI2CCTL_DEV_ADR	26	27	0x0c000000	0xf3ffffff	0x0
USB_GI2CCTL_DAT_SE0	28	28	0x10000000	0xefffffff	0x0
missing definiton	29	29	NA	NA	NA
USB_GI2CCTL_RW	30	30	0x40000000	0xbfffffff	0x0
USB_GI2CCTL_BSY_DNE	31	31	0x80000000	0x7fffffff	0x0

Register:USB_GPVNDCTL (0x7e980034)

field_name	start_bit	end_bit	set	clear	reset
USB_GPVNDCTL_REG_DATA	0	7	0x000000ff	0xffffff00	0x0
USB_GPVNDCTL_CTRL_UTMI	8	11	0x00000f00	0xfffff0ff	0x0
USB_GPVNDCTL_CTRL_ULPI	8	13	0x00003f00	0xffffc0ff	0x0
missing definiton	12	15	NA	NA	NA
missing definiton	14	7	NA	NA	NA
USB_GPVNDCTL_REG_ADDR	16	21	0x003f0000	0xffc0ffff	0x0
USB_GPVNDCTL_REG_WR	22	22	0x00400000	0xffbfffff	0x0
missing definiton	23	24	NA	NA	NA
USB_GPVNDCTL_NEW_REG_REQ	25	25	0x02000000	0xfdffffff	0x0
USB_GPVNDCTL_STS_BSY	26	26	0x04000000	0xfbffffff	0x0
USB_GPVNDCTL_STS_DONE	27	27	0x08000000	0xf7ffffff	0x0
missing definiton	28	30	NA	NA	NA
USB_GPVNDCTL_DIS_ULPI_DRVR	31	31	0x80000000	0x7fffffff	0x0

Register:USB_GGPIO (0x7e980038)

field_name	start_bit	end_bit	set	clear	reset
USB_GGPIO_GPI	0	15	0x0000ffff	0xffff0000	0x0
USB_GGPIO_GPO	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_GHWCFG2 (0x7e980048)

field_name	start_bit	end_bit	set	clear	reset
USB_GHWCFG2_MODE	0	2	0x00000007	0xfffffff8	0x0
USB_GHWCFG2_ARCHITECTURE	3	4	0x00000018	0xffffffe7	0x0
USB_GHWCFG2_SINGLE_POINT	5	5	0x00000020	0xffffffdf	0x0
USB_GHWCFG2_HSPHY_INTERFACE	6	7	0x000000c0	0xffffff3f	0x0
USB_GHWCFG2_FSPHY_INTERFACE	8	9	0x00000300	0xfffffcff	0x0
missing definiton	10	12	NA	NA	NA
missing definiton	11	16	NA	NA	NA
USB_GHWCFG2_NUM_EPS	13	10	0x0000000000	0xffffffff11	0x0
missing definiton	15	17	NA	NA	NA
USB_GHWCFG2_NUM_HOST_CHAN	17	14	0x0000000000	0xffffffff11	0x0
USB_GHWCFG2_EN_PERIO_HOST	18	18	0x00040000	0xfffbffff	0x0
USB_GHWCFG2_DFIFO_DYNAMIC	19	19	0x00080000	0xfff7ffff	0x0
missing definiton	20	21	NA	NA	NA
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH	22	23	0x00c00000	0xff3fffff	0x0
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH	24	25	0x03000000	0xfcffffff	0x0
USB_GHWCFG2_TOKEN_QUEUE_DEPTH	26	30	0x7c000000	0x83ffffff	0x0

Register:USB_GHWCFG3 (0x7e98004c)

field_name	start_bit	end_bit	set	clear	reset
USB_GHWCFG3_TRANS_COUNT_WIDTH	0	3	0x0000000f	0xfffffff0	0x0
USB_GHWCFG3_PACKET_COUNT_WIDTH	4	6	0x00000070	0xffffff8f	0x0
USB_GHWCFG3_MODE	7	7	0x00000080	0xffffff7f	0x0
USB_GHWCFG3_I2C_INTERFACE	8	8	0x00000100	0xfffffeff	0x0
USB_GHWCFG3_VENDOR_CTL_INTERFACE	9	9	0x00000200	0xfffffdff	0x0
USB_GHWCFG3_RM_OPT_FEATURES	10	10	0x00000400	0xfffffbff	0x0
USB_GHWCFG3_SYNC_RESET_TYPE	11	11	0x00000800	0xfffff7ff	0x0
missing definiton	12	15	NA	NA	NA
USB_GHWCFG3_DFIFO_DEPTH	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_GHWCFG4 (0x7e980050)

field_name	start_bit	end_bit	set	clear	reset
USB_GHWCFG4_NUM_PERIO_EPS	0	3	0x0000000f	0xfffffff0	0x0
USB_GHWCFG4_EN_PWROPT	4	4	0x00000010	0xffffffef	0x0
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60	5	5	0x00000020	0xffffffdf	0x0
missing definiton	6	13	NA	NA	NA
USB_GHWCFG4_HSPHY_DWIDTH	14	15	0x0000c000	0xffff3fff	0x0
USB_GHWCFG4_NUM_CRL_EPS	16	19	0x000f0000	0xfff0ffff	0x0
USB_GHWCFG4_EN_IDDIG_FILTER	20	20	0x00100000	0xffefffff	0x0
USB_GHWCFG4_EN_VBUSVALID_FILTER	21	21	0x00200000	0xffdfffff	0x0
USB_GHWCFG4_EN_A_VALID_FILTER	22	22	0x00400000	0xffbfffff	0x0
USB_GHWCFG4_EN_B_VALID_FILTER	23	23	0x00800000	0xff7fffff	0x0
USB_GHWCFG4_EN_SESSIONEND_FILTER	24	24	0x01000000	0xfeffffff	0x0
USB_GHWCFG4_EN_DED_TX_FIFO	25	25	0x02000000	0xfdffffff	0x0
USB_GHWCFG4_NUM_IN_EPS	26	27	0x0c000000	0xf3ffffff	0x0
missing definiton	28	29	NA	NA	NA
USB_GHWCFG4_EN_DESC_DMA	30	30	0x40000000	0xbfffffff	0x0
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC	31	31	0x80000000	0x7fffffff	0x0

Register:USB_DIEPTXF1 (0x7e980104)

field_name	start_bit	end_bit	set	clear	reset
USB_DIEPTXF1_FIFO_STADDR	0	15	0x0000ffff	0xffff0000	0x0
USB_DIEPTXF1_FIFO_SIZE	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_HCFG (0x7e980400)

field_name	start_bit	end_bit	set	clear	reset
USB_HCFG_LS_PHY_CLK_SEL	0	1	0x00000003	0xfffffffc	0x0
USB_HCFG_LS_SUPP	2	2	0x00000004	0xfffffffb	0x0

Register:USB_HFIR (0x7e980404)

field_name	start_bit	end_bit	set	clear	reset
USB_HFIR_IN	0	15	0x0000ffff	0xffff0000	0x0

Register:USB_HFNUM (0x7e980408)

field_name	start_bit	end_bit	set	clear	reset
USB_HFNUM_NUM	0	15	0x0000ffff	0xffff0000	0x0
USB_HFNUM_REM	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_HPTXSTS (0x7e980410)

field_name	start_bit	end_bit	set	clear	reset
USB_HPTXSTS_HPTXFSPCAVAIL	0	15	0x0000ffff	0xffff0000	0x0
USB_HPTXSTS_HPTXQSPCAVAIL	16	23	0x00ff0000	0xff00ffff	0x0
USB_HPTXSTS_HPTXQTOP	24	31	0xff000000	0x00ffffff	0x0

Register:USB_HPRT (0x7e980440)

field_name	start_bit	end_bit	set	clear	reset
USB_HPRT_CONN_STS	0	0	0x00000001	0xfffffffe	0x0
USB_HPRT_CONN_DET	1	1	0x00000002	0xfffffffd	0x0
USB_HPRT_ENA	2	2	0x00000004	0xfffffffb	0x0
USB_HPRT_EN_CHNG	3	3	0x00000008	0xfffffff7	0x0
USB_HPRT_OVR_CURR_ACT	4	4	0x00000010	0xffffffef	0x0
USB_HPRT_OVR_CURR_CHNG	5	5	0x00000020	0xffffffdf	0x0
USB_HPRT_RES	6	6	0x00000040	0xffffffbf	0x0
USB_HPRT_SUSP	7	7	0x00000080	0xffffff7f	0x0
USB_HPRT_RST	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	9	NA	NA	NA
USB_HPRT_LN_STS	10	11	0x00000c00	0xfffff3ff	0x0
USB_HPRT_PWR	12	12	0x00001000	0xffffefff	0x0
USB_HPRT_TST_CTL	13	16	0x0001e000	0xfffe1fff	0x0
USB_HPRT_SPD	17	18	0x00060000	0xfff9ffff	0x0

Register:USB_HCCHAR0 (0x7e980500)

field_name	start_bit	end_bit	set	clear	reset
USB_HCCHAR0_MPS	0	10	0x000007ff	0xfffff800	0x0
USB_HCCHAR0_EP_NUM	11	14	0x00007800	0xffff87ff	0x0
USB_HCCHAR0_EP_DIR	15	15	0x00008000	0xffff7fff	0x0
missing definiton	16	16	NA	NA	NA
USB_HCCHAR0_LSPD_DEV	17	17	0x00020000	0xfffdffff	0x0
USB_HCCHAR0_EP_TYPE	18	19	0x000c0000	0xfff3ffff	0x0
USB_HCCHAR0_MC_EC	20	21	0x00300000	0xffcfffff	0x0
USB_HCCHAR0_DEV_ADDR	22	28	0x1fc00000	0xe03fffff	0x0
USB_HCCHAR0_ODD_FRM	29	29	0x20000000	0xdfffffff	0x0
USB_HCCHAR0_CH_DIS	30	30	0x40000000	0xbfffffff	0x0
USB_HCCHAR0_CH_ENA	31	31	0x80000000	0x7fffffff	0x0

Register:USB_HCSPLT0 (0x7e980504)

field_name	start_bit	end_bit	set	clear	reset
USB_HCSPLT0_PRT_ADDR	0	6	0x0000007f	0xffffff80	0x0
USB_HCSPLT0_HUB_ADDR	7	13	0x00003f80	0xffffc07f	0x0
USB_HCSPLT0_XACT_POS	14	15	0x0000c000	0xffff3fff	0x0
USB_HCSPLT0_COMP_SPLT	16	16	0x00010000	0xfffeffff	0x0
missing definiton	17	30	NA	NA	NA
USB_HCSPLT0_SPLT_ENA	31	31	0x80000000	0x7fffffff	0x0

Register:USB_HCINT0 (0x7e980508)

field_name	start_bit	end_bit	set	clear	reset
USB_HCINT0_XFER_COMPL	0	0	0x00000001	0xfffffffe	0x0
USB_HCINT0_CH_HLTD	1	1	0x00000002	0xfffffffd	0x0
USB_HCINT0_AHB_ERR	2	2	0x00000004	0xfffffffb	0x0
USB_HCINT0_STALL	3	3	0x00000008	0xfffffff7	0x0
USB_HCINT0_NAK	4	4	0x00000010	0xffffffef	0x0
USB_HCINT0_ACK	5	5	0x00000020	0xffffffdf	0x0
USB_HCINT0_NYET	6	6	0x00000040	0xffffffbf	0x0
USB_HCINT0_XACT_ERR	7	7	0x00000080	0xffffff7f	0x0
USB_HCINT0_BBL_ERR	8	8	0x00000100	0xfffffeff	0x0
USB_HCINT0_FRM_OVRUN	9	9	0x00000200	0xfffffdff	0x0
USB_HCINT0_DATA_TGL_ERR	10	10	0x00000400	0xfffffbff	0x0

Register:USB_HCTSIZ0 (0x7e980510)

field_name	start_bit	end_bit	set	clear	reset
USB_HCTSIZ0_XFER_SIZE	0	18	0x0007ffff	0xfff80000	0x0
USB_HCTSIZ0_PKT_CNT	19	28	0x1ff80000	0xe007ffff	0x0
USB_HCTSIZ0_PID	29	30	0x60000000	0x9fffffff	0x0
USB_HCTSIZ0_DO_PNG	31	31	0x80000000	0x7fffffff	0x0

Register:USB_DCFG (0x7e980800)

field_name	start_bit	end_bit	set	clear	reset
USB_DCFG_DEV_SPD	0	1	0x00000003	0xfffffffc	0x0
USB_DCFG_NZ_STS_OUT_HSHK	2	2	0x00000004	0xfffffffb	0x0
missing definiton	3	3	NA	NA	NA
USB_DCFG_DEV_ADDR	4	10	0x000007f0	0xfffff80f	0x0
USB_DCFG_PER_FR_INT	11	12	0x00001800	0xffffe7ff	0x0
missing definiton	13	17	NA	NA	NA
USB_DCFG_EP_MIS_CNT	18	22	0x007c0000	0xff83ffff	0x0
USB_DCFG_DESC_DMA	23	23	0x00800000	0xff7fffff	0x0
USB_DCFG_PER_SCH_INTV	24	25	0x03000000	0xfcffffff	0x0

Register:USB_DCTL (0x7e980804)

field_name	start_bit	end_bit	set	clear	reset
USB_DCTL_RMT_WKUP_SIG	0	0	0x00000001	0xfffffffe	0x0
USB_DCTL_SFT_DISCON	1	1	0x00000002	0xfffffffd	0x0
USB_DCTL_GNP_IN_NAK_STS	2	2	0x00000004	0xfffffffb	0x0
USB_DCTL_GOUT_NAK_STS	3	3	0x00000008	0xfffffff7	0x0
USB_DCTL_TST_CTL	4	6	0x00000070	0xffffff8f	0x0
USB_DCTL_SGNP_IN_NAK	7	7	0x00000080	0xffffff7f	0x0
USB_DCTL_CGNP_IN_NAK	8	8	0x00000100	0xfffffeff	0x0
USB_DCTL_SGOUT_NAK	9	9	0x00000200	0xfffffdff	0x0
USB_DCTL_CGOUT_NAK	10	10	0x00000400	0xfffffbff	0x0
USB_DCTL_PWRON_PRG_DONE	11	11	0x00000800	0xfffff7ff	0x0
missing definiton	12	12	NA	NA	NA
USB_DCTL_GMC	13	14	0x00006000	0xffff9fff	0x0
USB_DCTL_IGN_FRM_NUM	15	15	0x00008000	0xffff7fff	0x0

Register:USB_DSTS (0x7e980808)

field_name	start_bit	end_bit	set	clear	reset
USB_DSTS_SUSP_STS	0	0	0x00000001	0xfffffffe	0x0
USB_DSTS_ENUM_SPD	1	2	0x00000006	0xfffffff9	0x0
USB_DSTS_ERRTIC_ERR	3	3	0x00000008	0xfffffff7	0x0
missing definiton	4	7	NA	NA	NA
USB_DSTS_SOF_FN	8	21	0x003fff00	0xffc000ff	0x0

Register:USB_DAINT (0x7e980818)

field_name	start_bit	end_bit	set	clear	reset
USB_DAINT_IN_EP_INT	0	15	0x0000ffff	0xffff0000	0x0
USB_DAINT_OUT_EP_INT	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_DVBUSPULSE (0x7e98082c)

field_name	start_bit	end_bit	set	clear	reset
USB_DVBUSPULSE_PULSE	0	11	0x00000fff	0xfffff000	0x0

Register:USB_DTHRCTL (0x7e980830)

field_name	start_bit	end_bit	set	clear	reset
USB_DTHRCTL_NON_ISO_THR_EN	0	0	0x00000001	0xfffffffe	0x0
USB_DTHRCTL_ISO_THR_EN	1	1	0x00000002	0xfffffffd	0x0
USB_DTHRCTL_TX_THR_LEN	2	10	0x000007fc	0xfffff803	0x0
missing definiton	11	15	NA	NA	NA
USB_DTHRCTL_RX_THR_EN	16	16	0x00010000	0xfffeffff	0x0
USB_DTHRCTL_RX_THR_LEN	17	26	0x07fe0000	0xf801ffff	0x0
USB_DTHRCTL_ARB_PRK_EN	27	27	0x08000000	0xf7ffffff	0x0

Register:USB_DIEPEMPMSK (0x7e980834)

field_name	start_bit	end_bit	set	clear	reset
USB_DIEPEMPMSK_EP_TXF_EMP_MSK	0	15	0x0000ffff	0xffff0000	0x0

Register:USB_DIEPCTL0 (0x7e980900)

field_name	start_bit	end_bit	set	clear	reset
USB_DIEPCTL0_MPS	0	10	0x000007ff	0xfffff800	0x0
USB_DIEPCTL0_NEXT_EP	11	14	0x00007800	0xffff87ff	0x0
USB_DIEPCTL0_USB_ACT_EP	15	15	0x00008000	0xffff7fff	0x0
USB_DIEPCTL0_EO_FR_NUM	16	16	0x00010000	0xfffeffff	0x0
USB_DIEPCTL0_DPID	16	16	0x00010000	0xfffeffff	0x0
USB_DIEPCTL0_NAK_STS	17	17	0x00020000	0xfffdffff	0x0
missing definiton	17	15	NA	NA	NA
USB_DIEPCTL0_TYPE	18	19	0x000c0000	0xfff3ffff	0x0
USB_DIEPCTL0_SNP	20	20	0x00100000	0xffefffff	0x0
USB_DIEPCTL0_STALL	21	21	0x00200000	0xffdfffff	0x0
USB_DIEPCTL0_TXF_NUM	22	25	0x03c00000	0xfc3fffff	0x0
USB_DIEPCTL0_CNAK	26	26	0x04000000	0xfbffffff	0x0
USB_DIEPCTL0_SNAK	27	27	0x08000000	0xf7ffffff	0x0
USB_DIEPCTL0_SET_EVEN_FR	28	28	0x10000000	0xefffffff	0x0
USB_DIEPCTL0_SET_D0_PID	28	28	0x10000000	0xefffffff	0x0
missing definiton	29	27	NA	NA	NA
USB_DIEPCTL0_SET_ODD_FR	29	29	0x20000000	0xdfffffff	0x0
USB_DIEPCTL0_SET_D1_PID	29	29	0x20000000	0xdfffffff	0x0
USB_DIEPCTL0_DIS	30	30	0x40000000	0xbfffffff	0x0
missing definiton	30	28	NA	NA	NA
USB_DIEPCTL0_ENA	31	31	0x80000000	0x7fffffff	0x0

Register:USB_DIEPINT0 (0x7e980908)

field_name	start_bit	end_bit	set	clear	reset
USB_DIEPINT0_XFER_COMPL	0	0	0x00000001	0xfffffffe	0x0
USB_DIEPINT0_EP_DISBLD	1	1	0x00000002	0xfffffffd	0x0
USB_DIEPINT0_AHB_ERR	2	2	0x00000004	0xfffffffb	0x0
USB_DIEPINT0_SETUP	3	3	0x00000008	0xfffffff7	0x0
USB_DIEPINT0_TIMEOUT	3	3	0x00000008	0xfffffff7	0x0
USB_DIEPINT0_IN_TKN_TXFEMP	4	4	0x00000010	0xffffffef	0x0
missing definiton	4	2	NA	NA	NA
USB_DIEPINT0_OUT_TKN_EP_DIS	4	4	0x00000010	0xffffffef	0x0
missing definiton	5	3	NA	NA	NA
USB_DIEPINT0_STS_PHSE_RCVD	5	5	0x00000020	0xffffffdf	0x0
USB_DIEPINT0_IN_TKN_EP_MIS	5	5	0x00000020	0xffffffdf	0x0
USB_DIEPINT0_IN_EP_NAK_EFF	6	6	0x00000040	0xffffffbf	0x0
USB_DIEPINT0_BACK2BACK_SETUP	6	6	0x00000040	0xffffffbf	0x0
missing definiton	6	4	NA	NA	NA
USB_DIEPINT0_TXF_EMPTY	7	7	0x00000080	0xffffff7f	0x0
missing definiton	7	5	NA	NA	NA
USB_DIEPINT0_TX_FIFO_UNDRN	8	8	0x00000100	0xfffffeff	0x0
USB_DIEPINT0_OUT_PKT_ERR	8	8	0x00000100	0xfffffeff	0x0
missing definiton	9	7	NA	NA	NA
USB_DIEPINT0_BNA	9	9	0x00000200	0xfffffdff	0x0

Register:USB_DIEPTSIZ0 (0x7e980910)

field_name	start_bit	end_bit	set	clear	reset
USB_DIEPTSIZ0_XFERSIZE	0	18	0x0007ffff	0xfff80000	0x0
USB_DIEPTSIZ0_PKT_CNT	19	28	0x1ff80000	0xe007ffff	0x0
USB_DIEPTSIZ0_MC	29	30	0x60000000	0x9fffffff	0x0
USB_DIEPTSIZ0_SUP_CNT	29	30	0x60000000	0x9fffffff	0x0
USB_DIEPTSIZ0_RX_DPID	29	30	0x60000000	0x9fffffff	0x0
missing definiton	31	28	NA	NA	NA

Register:USB_DTXFSTS0 (0x7e980918)

field_name	start_bit	end_bit	set	clear	reset
missing definiton	0	15	NA	NA	NA
USB_DTXFSTS0_SPC_AVAIL	16	31	0xffff0000	0x0000ffff	0x0

Register:USB_DOEPCTL0 (0x7e980b00)

field_name	start_bit	end_bit	set	clear	reset
USB_DOEPCTL0_MPS	0	10	0x000007ff	0xfffff800	0x0
USB_DOEPCTL0_NEXT_EP	11	14	0x00007800	0xffff87ff	0x0
USB_DOEPCTL0_USB_ACT_EP	15	15	0x00008000	0xffff7fff	0x0
USB_DOEPCTL0_DPID	16	16	0x00010000	0xfffeffff	0x0
USB_DOEPCTL0_EO_FR_NUM	16	16	0x00010000	0xfffeffff	0x0
USB_DOEPCTL0_NAK_STS	17	17	0x00020000	0xfffdffff	0x0
missing definiton	17	15	NA	NA	NA
USB_DOEPCTL0_TYPE	18	19	0x000c0000	0xfff3ffff	0x0
USB_DOEPCTL0_SNP	20	20	0x00100000	0xffefffff	0x0
USB_DOEPCTL0_STALL	21	21	0x00200000	0xffdfffff	0x0
USB_DOEPCTL0_TXF_NUM	22	25	0x03c00000	0xfc3fffff	0x0
USB_DOEPCTL0_CNAK	26	26	0x04000000	0xfbffffff	0x0
USB_DOEPCTL0_SNAK	27	27	0x08000000	0xf7ffffff	0x0
USB_DOEPCTL0_SET_D0_PID	28	28	0x10000000	0xefffffff	0x0
USB_DOEPCTL0_SET_EVEN_FR	28	28	0x10000000	0xefffffff	0x0
USB_DOEPCTL0_SET_D1_PID	29	29	0x20000000	0xdfffffff	0x0
missing definiton	29	27	NA	NA	NA
USB_DOEPCTL0_SET_ODD_FR	29	29	0x20000000	0xdfffffff	0x0
USB_DOEPCTL0_DIS	30	30	0x40000000	0xbfffffff	0x0
missing definiton	30	28	NA	NA	NA
USB_DOEPCTL0_ENA	31	31	0x80000000	0x7fffffff	0x0

Register:USB_DOEPINT0 (0x7e980b08)

field_name	start_bit	end_bit	set	clear	reset
USB_DOEPINT0_XFER_COMPL	0	0	0x00000001	0xfffffffe	0x0
USB_DOEPINT0_EP_DISBLD	1	1	0x00000002	0xfffffffd	0x0
USB_DOEPINT0_AHB_ERR	2	2	0x00000004	0xfffffffb	0x0
USB_DOEPINT0_TIMEOUT	3	3	0x00000008	0xfffffff7	0x0
USB_DOEPINT0_SETUP	3	3	0x00000008	0xfffffff7	0x0
USB_DOEPINT0_OUT_TKN_EP_DIS	4	4	0x00000010	0xffffffef	0x0
USB_DOEPINT0_IN_TKN_TXFEMP	4	4	0x00000010	0xffffffef	0x0
missing definiton	4	2	NA	NA	NA
missing definiton	5	3	NA	NA	NA
USB_DOEPINT0_STS_PHSE_RCVD	5	5	0x00000020	0xffffffdf	0x0
USB_DOEPINT0_IN_TKN_EP_MIS	5	5	0x00000020	0xffffffdf	0x0
USB_DOEPINT0_IN_EP_NAK_EFF	6	6	0x00000040	0xffffffbf	0x0
missing definiton	6	4	NA	NA	NA
USB_DOEPINT0_BACK2BACK_SETUP	6	6	0x00000040	0xffffffbf	0x0
missing definiton	7	5	NA	NA	NA
USB_DOEPINT0_TXF_EMPTY	7	7	0x00000080	0xffffff7f	0x0
USB_DOEPINT0_TX_FIFO_UNDRN	8	8	0x00000100	0xfffffeff	0x0
USB_DOEPINT0_OUT_PKT_ERR	8	8	0x00000100	0xfffffeff	0x0
USB_DOEPINT0_BNA	9	9	0x00000200	0xfffffdff	0x0
missing definiton	9	7	NA	NA	NA

Register:USB_DOEPTSIZ0 (0x7e980b10)

field_name	start_bit	end_bit	set	clear	reset
USB_DOEPTSIZ0_XFERSIZE	0	18	0x0007ffff	0xfff80000	0x0
USB_DOEPTSIZ0_PKT_CNT	19	28	0x1ff80000	0xe007ffff	0x0
USB_DOEPTSIZ0_MC	29	30	0x60000000	0x9fffffff	0x0
USB_DOEPTSIZ0_SUP_CNT	29	30	0x60000000	0x9fffffff	0x0
USB_DOEPTSIZ0_RX_DPID	29	30	0x60000000	0x9fffffff	0x0
missing definiton	31	28	NA	NA	NA

Register:USB_PCGCR (0x7e980e00)

field_name	start_bit	end_bit	set	clear	reset
USB_PCGCR_STOP_PCLK	0	0	0x00000001	0xfffffffe	0x0
USB_PCGCR_GATE_HCLK	1	1	0x00000002	0xfffffffd	0x0
USB_PCGCR_PWR_CLMP	2	2	0x00000004	0xfffffffb	0x0
USB_PCGCR_RST_PDWN_MODULE	3	3	0x00000008	0xfffffff7	0x0

V3D

Info

base	0x7ec00000

Registers

register name	address	type	width	mask
V3D_IDENT0	0x7ec00000	RW	32	0xffffffff
V3D_IDENT1	0x7ec00004	RW	32	0xffffffff
V3D_IDENT2	0x7ec00008	RW	32	0xffffffff
V3D_IDENT3	0x7ec0000c	RW	32	0xffffffff
V3D_SCRATCH	0x7ec00010	RW	32	0xffffffff
V3D_L2CACTL	0x7ec00020	RW	32	0xffffffff
V3D_SLCACTL	0x7ec00024	RW	32	0xffffffff
V3D_INTCTL	0x7ec00030	RW	32	0xffffffff
V3D_INTENA	0x7ec00034	RW	32	0xffffffff
V3D_INTDIS	0x7ec00038	RW	32	0xffffffff
V3D_CT0CS	0x7ec00100	RW	32	0xffffffff
V3D_CT1CS	0x7ec00104	RW	32	0xffffffff
V3D_CT0EA	0x7ec00108	RW	32	0xffffffff
V3D_CT1EA	0x7ec0010c	RW	32	0xffffffff
V3D_CT0CA	0x7ec00110	RW	32	0xffffffff
V3D_CT1CA	0x7ec00114	RW	32	0xffffffff
V3D_CT00RA0	0x7ec00118	RW	32	0xffffffff
V3D_CT01RA0	0x7ec0011c	RW	32	0xffffffff
V3D_CT0LC	0x7ec00120	RW	32	0xffffffff
V3D_CT1LC	0x7ec00124	RW	32	0xffffffff
V3D_CT0PC	0x7ec00128	RW	32	0xffffffff
V3D_CT1PC	0x7ec0012c	RW	32	0xffffffff
V3D_PCS	0x7ec00130	RW	9	0x0000013f
V3D_BFC	0x7ec00134	RW	8	0x000000ff
V3D_RFC	0x7ec00138	RW	8	0x000000ff
V3D_BPCA	0x7ec00300	RW	32	0xffffffff
V3D_BPCS	0x7ec00304	RW	32	0xffffffff
V3D_BPOA	0x7ec00308	RW	32	0xffffffff
V3D_BPOS	0x7ec0030c	RW	32	0xffffffff
V3D_BXCF	0x7ec00310	RW	2	0x00000003
V3D_SQRSV0	0x7ec00410	RW	32	0xffffffff
V3D_SQRSV1	0x7ec00414	RW	32	0xffffffff
V3D_SQCNTL	0x7ec00418	RW	4	0x0000000f
V3D_SQCSTAT	0x7ec0041c	RW	32	0xffffffff
V3D_SRQPC	0x7ec00430	RW	32	0xffffffff
V3D_SRQUA	0x7ec00434	RW	32	0xffffffff
V3D_SRQUL	0x7ec00438	RW	12	0x00000fff
V3D_SRQCS	0x7ec0043c	RW	24	0x00ffffbf
V3D_VPACNTL	0x7ec00500	RW	32	0xffffffff
V3D_VPMBASE	0x7ec00504	RW	32	0xffffffff
V3D_PCTRC	0x7ec00670	RW	16	0x0000ffff
V3D_PCTRE	0x7ec00674	RW	32	0x8000ffff
V3D_PCTR0	0x7ec00680	RW	32	0xffffffff
V3D_PCTRS0	0x7ec00684	RW	5	0x0000001f
V3D_PCTR1	0x7ec00688	RW	32	0xffffffff
V3D_PCTRS1	0x7ec0068c	RW	5	0x0000001f
V3D_PCTR2	0x7ec00690	RW	32	0xffffffff
V3D_PCTRS2	0x7ec00694	RW	5	0x0000001f
V3D_PCTR3	0x7ec00698	RW	32	0xffffffff
V3D_PCTRS3	0x7ec0069c	RW	5	0x0000001f
V3D_PCTR4	0x7ec006a0	RW	32	0xffffffff
V3D_PCTRS4	0x7ec006a4	RW	5	0x0000001f
V3D_PCTR5	0x7ec006a8	RW	32	0xffffffff
V3D_PCTRS5	0x7ec006ac	RW	5	0x0000001f
V3D_PCTR6	0x7ec006b0	RW	32	0xffffffff
V3D_PCTRS6	0x7ec006b4	RW	5	0x0000001f
V3D_PCTR7	0x7ec006b8	RW	32	0xffffffff
V3D_PCTRS7	0x7ec006bc	RW	5	0x0000001f
V3D_PCTR8	0x7ec006c0	RW	32	0xffffffff
V3D_PCTRS8	0x7ec006c4	RW	5	0x0000001f
V3D_PCTR9	0x7ec006c8	RW	32	0xffffffff
V3D_PCTRS9	0x7ec006cc	RW	5	0x0000001f
V3D_PCTR10	0x7ec006d0	RW	32	0xffffffff
V3D_PCTRS10	0x7ec006d4	RW	5	0x0000001f
V3D_PCTR11	0x7ec006d8	RW	32	0xffffffff
V3D_PCTRS11	0x7ec006dc	RW	5	0x0000001f
V3D_PCTR12	0x7ec006e0	RW	32	0xffffffff
V3D_PCTRS12	0x7ec006e4	RW	5	0x0000001f
V3D_PCTR13	0x7ec006e8	RW	32	0xffffffff
V3D_PCTRS13	0x7ec006ec	RW	5	0x0000001f
V3D_PCTR14	0x7ec006f0	RW	32	0xffffffff
V3D_PCTRS14	0x7ec006f4	RW	5	0x0000001f
V3D_PCTR15	0x7ec006f8	RW	32	0xffffffff
V3D_PCTRS15	0x7ec006fc	RW	5	0x0000001f
V3D_DBCFG	0x7ec00e00	RW	32	0xffffffff
V3D_DBSCS	0x7ec00e04	RW	32	0xffffffff
V3D_DBSCFG	0x7ec00e08	RW	32	0xffffffff
V3D_DBSSR	0x7ec00e0c	RW	32	0xffffffff
V3D_DBSDR0	0x7ec00e10	RW	32	0xffffffff
V3D_DBSDR1	0x7ec00e14	RW	32	0xffffffff
V3D_DBSDR2	0x7ec00e18	RW	32	0xffffffff
V3D_DBSDR3	0x7ec00e1c	RW	32	0xffffffff
V3D_DBQRUN	0x7ec00e20	RW	32	0xffffffff
V3D_DBQHLT	0x7ec00e24	RW	32	0xffffffff
V3D_DBQSTP	0x7ec00e28	RW	32	0xffffffff
V3D_DBQITE	0x7ec00e2c	RW	32	0xffffffff
V3D_DBQITC	0x7ec00e30	RW	32	0xffffffff
V3D_DBQGHC	0x7ec00e34	RW	32	0xffffffff
V3D_DBQGHG	0x7ec00e38	RW	32	0xffffffff
V3D_DBQGHH	0x7ec00e3c	RW	32	0xffffffff
V3D_DBGE	0x7ec00f00	RW	32	0xffffffff
V3D_FDBG0	0x7ec00f04	RW	32	0xffffffff
V3D_FDBGB	0x7ec00f08	RW	32	0xffffffff
V3D_FDBGR	0x7ec00f0c	RW	32	0xffffffff
V3D_FDBGS	0x7ec00f10	RW	32	0xffffffff
V3D_ERRSTAT	0x7ec00f20	RW	32	0xffffffff

Unsupported defines

define	value
V3D_BASE_ADDRESS	0x1A005000
V3D_MEM1_BASE_ADDRESS	0x1A00B000
V3D_MEM2_BASE_ADDRESS	0x1A00C000

VCE

Info

base	0x7f100000

Registers

register name	address	type
VCE_DATA_MEM_BASE	0x7f100000	RW
VCE_PROGRAM_MEM_BASE	0x7f110000	RW
VCE_REGISTERS_BASE	0x7f120000	RW
VCE_STATUS	0x7f140000	RW
VCE_VERSION	0x7f140004	RW
VCE_PC_PF0	0x7f140008	RW
VCE_PC_IF0	0x7f14000c	RW
VCE_PC_RD0	0x7f140010	RW
VCE_PC_EX0	0x7f140014	RW
VCE_CONTROL	0x7f140020	RW
VCE_SEMA_CLEAR	0x7f140024	RW
VCE_SEMA_SET	0x7f140028	RW
VCE_BAD_ADDR	0x7f140030	RW
VCE_SIM_DEBUG_OPTIONS	0x7f140100	RW

Unsupported defines

define	value
VCE_BAD_ADDR_OFFSET	0x40030
VCE_BUSY_BKPT	0x00
VCE_BUSY_DMAIN	0x08
VCE_BUSY_DMAOUT	0x09
VCE_BUSY_MEMSYNC	0x0a
VCE_BUSY_SLEEP	0x0b
VCE_BUSY_USER	0x01
VCE_CONTROL_CLEAR_RUN	0
VCE_CONTROL_OFFSET	0x40020
VCE_CONTROL_SET_RUN	1
VCE_CONTROL_SINGLE_STEP	3
VCE_DATA_MEM_OFFSET	0
VCE_DATA_MEM_SIZE	0x2000
VCE_PC_EX0_OFFSET	0x40014
VCE_PC_IF0_OFFSET	0x4000c
VCE_PC_PF0_OFFSET	0x40008
VCE_PC_RD0_OFFSET	0x40010
VCE_PROGRAM_MEM_OFFSET	0x10000
VCE_PROGRAM_MEM_SIZE	0x4000
VCE_REASON_RESET	0x12
VCE_REASON_RUNNING	0x11
VCE_REASON_SINGLE	0x13
VCE_REASON_STOPPED	0x10
VCE_REGISTERS_COUNT	63
VCE_REGISTERS_OFFSET	0x20000
VCE_SEMA_CLEAR_OFFSET	0x40024
VCE_SEMA_COUNT	8
VCE_SEMA_SET_OFFSET	0x40028
VCE_SIM_DEBUG_OPTIONS_OFFSET	0x40100
VCE_STATUS_BUSYBITS_MASK	0xffff
VCE_STATUS_INTERRUPT_POS	31
VCE_STATUS_NANOFLAG_POS	25
VCE_STATUS_OFFSET	0x40000
VCE_STATUS_REASON_MASK	0x1f
VCE_STATUS_REASON_POS	16
VCE_STATUS_RUNNING_POS	24
VCE_VERSION_OFFSET	0x40004

VEC

Info

base	0x7e806000

Registers

register name	address	type	width	mask
VEC_CGMSAE_RESET	0x7e806040	RW	32	0xffffffff
VEC_CGMSAE_TOP_CONTROL	0x7e806044	RW	32	0xffffffff
VEC_CGMSAE_BOT_CONTROL	0x7e806048	RW	32	0xffffffff
VEC_CGMSAE_TOP_FORMAT	0x7e80604c	RW	32	0xffffffff
VEC_CGMSAE_BOT_FORMAT	0x7e806050	RW	32	0xffffffff
VEC_CGMSAE_TOP_DATA	0x7e806054	RW	32	0xffffffff
VEC_CGMSAE_BOT_DATA	0x7e806058	RW	32	0xffffffff
VEC_CGMSAE_REVID	0x7e80605c	RW	32	0xffffffff
VEC_ENC_RevID	0x7e806060	RW	32	0xffffffff
VEC_ENC_PrimaryControl	0x7e806068	RW	32	0xffffffff
VEC_WSE_RESET	0x7e8060c0	RW	32	0xffffffff
VEC_WSE_CONTROL	0x7e8060c4	RW	32	0xffffffff
VEC_WSE_WSS_DATA	0x7e8060c8	RW	32	0xffffffff
VEC_WSE_VPS_DATA_1	0x7e8060cc	RW	32	0xffffffff
VEC_WSE_VPS_CONTROL	0x7e8060d0	RW	32	0xffffffff
VEC_REVID	0x7e806100	RW	32	0xffffffff
VEC_CONFIG0	0x7e806104	RW	32	0xffffffff
VEC_SCHPH	0x7e806108	RW	32	0xffffffff
VEC_SOFT_RESET	0x7e80610c	RW	32	0xffffffff
VEC_CPS01_CPS23	0x7e806120	RW	32	0xffffffff
VEC_CPS45_CPS67	0x7e806124	RW	32	0xffffffff
VEC_CPS89_CPS1011	0x7e806128	RW	32	0xffffffff
VEC_CPS1213_CPS1415	0x7e80612c	RW	32	0xffffffff
VEC_CPS1617_CPS1819	0x7e806130	RW	32	0xffffffff
VEC_CPS2021_CPS2223	0x7e806134	RW	32	0xffffffff
VEC_CPS2425_CPS2627	0x7e806138	RW	32	0xffffffff
VEC_CPS2829_CPS3031	0x7e80613c	RW	32	0xffffffff
VEC_CPS32_CPC	0x7e806140	RW	32	0xffffffff
VEC_CLMP0_START	0x7e806144	RW	32	0xffffffff
VEC_CLMP0_END	0x7e806148	RW	32	0xffffffff
VEC_FREQ3_2	0x7e806180	RW	32	0xffffffff
VEC_FREQ1_0	0x7e806184	RW	32	0xffffffff
VEC_CONFIG1	0x7e806188	RW	32	0xffffffff
VEC_CONFIG2	0x7e80618c	RW	32	0xffffffff
VEC_INTERRUPT_CONTROL	0x7e806190	RW	32	0xffffffff
VEC_INTERRUPT_STATUS	0x7e806194	RW	32	0xffffffff
VEC_FCW_SECAM_B	0x7e806198	RW	32	0xffffffff
VEC_SECAM_GAIN_VAL	0x7e80619c	RW	32	0xffffffff
VEC_CONFIG3	0x7e8061a0	RW	32	0xffffffff
VEC_CONFIG4	0x7e8061a4	RW	32	0xffffffff
VEC_STATUS0	0x7e806200	RW	32	0xffffffff
VEC_MASK0	0x7e806204	RW	32	0xffffffff
VEC_CFG	0x7e806208	RW	32	0xffffffff
VEC_DAC_TEST	0x7e80620c	RW	32	0xffffffff
VEC_DAC_CONFIG	0x7e806210	RW	32	0xffffffff
VEC_DAC_MISC	0x7e806214	RW	32	0xffffffff

Unsupported defines

define	value
VEC_BASE_ADDRESS	0x7e806000

VPU_ARB_CTRL

Info

base	0x7ee04000

Registers

register name	address	type	width	mask	reset
VPU_ARB_CTRL_UC	0x7ee04000	RW	16	0x0000ffff	0000000000
VPU_ARB_CTRL_L2	0x7ee04004	RW	16	0x0000ffff	0000000000

Register:VPU_ARB_CTRL_UC (0x7ee04000)

field_name	start_bit	end_bit	set	clear	reset
VPU_ARB_CTRL_UC_LIMIT	0	1	0x00000003	0xfffffffc	0x0
VPU_ARB_CTRL_UC_DELAY	2	3	0x0000000c	0xfffffff3	0x0
VPU_ARB_CTRL_UC_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
VPU_ARB_CTRL_UC_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
VPU_ARB_CTRL_UC_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0

Register:VPU_ARB_CTRL_L2 (0x7ee04004)

field_name	start_bit	end_bit	set	clear	reset
VPU_ARB_CTRL_L2_LIMIT	0	1	0x00000003	0xfffffffc	0x0
VPU_ARB_CTRL_L2_DELAY	2	3	0x0000000c	0xfffffff3	0x0
VPU_ARB_CTRL_L2_THRESHOLD	4	5	0x00000030	0xffffffcf	0x0
VPU_ARB_CTRL_L2_ALGORITHM	6	7	0x000000c0	0xffffff3f	0x0
VPU_ARB_CTRL_L2_CHANNEL_INIBIT	8	15	0x0000ff00	0xffff00ff	0x0