source code

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Examples:

Source

Instruction set

  • Arithmetic

        OP1, OP2 := Register or Immediate value.
        DST := Register.
    • ADD OP1, OP2, DST
    • SUB OP1, OP2, DST
    • MUL OP1, OP2, DST
    • DIV OP1, OP2, DST

  • Flow control

        ADDR:= Instruction address (row #).
    • JMP ADDR
    • JZ  ADDR
    • JNZ ADDR

  • Memory interface

        REG := Register
        VAL, ADDR := Register or Immediate value.
    • LDR ADDR, REG
          Page size := 1.
    • STR VAL, ADDR

  • Extra

    • ; comment
load
configuration
Register File
registers #
Functional Units
adders # latency
multipliers # latency
divider # latency
Memory
read latency
write latency
Cache
algorithm
N (ways) size
read latency write latency
Pipeline
issue-exec delay
exec-write delay
ROB (0 = disabled)size
Branch Predictor
kind
N (bits)
K (size)
apply
execution
0   0
Source Code
# Instruction
0MUL 1,5,R0
1MUL 2,5,R1
2ADD 1,R5,R5
3MUL 4,5,R3
4SUB R5,5,R6
5JNZ 0
6EOF
Execution
# Instruction Issue Exec Write Commit
reorder buffer
tagInstructiondstvalrdyrow
0
1
2
3
4
5
6
7
Reservation Stations
Name Busy Op Vj Vk Qj Qk tag due
ADDR0
ADDR1
ADDR2
MULT0
MULT1
DIV0
MEM0
Register Status (Qi)
R0R1R2R3
0-0-0-0-
R4R5R6R7
0-0-0-0-


cache
N:0N:1
addrvaldirtyaddrvaldirty
0
1
hit NaN% - evictions 0